37 	u32 nf;  member
46 	.nf = _nf,					\
213 	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
241 	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;  in rkclk_set_pll()
245 	      (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);  in rkclk_set_pll()
252 	rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);  in rkclk_set_pll()
258 		rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);  in rkclk_set_pll()
272 	u32 nr, no, nf;  in rkclk_pll_get_rate()  local
293 		nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;  in rkclk_pll_get_rate()
295 		return (24 * nf / (nr * no)) * 1000000;  in rkclk_pll_get_rate()
306 		{.nf = 25, .nr = 2, .no = 1},  in rkclk_configure_ddr()
307 		{.nf = 400, .nr = 9, .no = 2},  in rkclk_configure_ddr()
308 		{.nf = 500, .nr = 9, .no = 2},  in rkclk_configure_ddr()
309 		{.nf = 100, .nr = 3, .no = 1},  in rkclk_configure_ddr()
358 	uint ref_khz = OSC_HZ / 1000, nr, nf = 0;  in pll_para_config()  local
380 		div->nf = best_div->nf;  in pll_para_config()
410 		nf = vco_khz / fref_khz;  in pll_para_config()
411 		if (nf >= max_nf)  in pll_para_config()
413 		diff_khz = vco_khz - nf * fref_khz;  in pll_para_config()
414 		if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {  in pll_para_config()
415 			nf++;  in pll_para_config()
424 		div->nf = nf;  in pll_para_config()