| /rk3399_rockchip-uboot/post/lib_powerpc/ |
| H A D | asm.S | 27 mr r3, r4
28 mr r4, r5
50 mr r3, r4
51 mr r4, r5
52 mr r5, r6
73 mr r3, r5
74 mr r4, r6
94 mr r3, r5
120 mr r3, r6
150 mr r3, r6
[all …]
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| /rk3399_rockchip-uboot/arch/arm/mach-at91/ |
| H A D | sdram.c | 38 writel(AT91_SDRAMC_MODE_NOP, ®->mr); in sdramc_initialize()
42 writel(AT91_SDRAMC_MODE_PRECHARGE, ®->mr); in sdramc_initialize()
50 writel(AT91_SDRAMC_MODE_REFRESH, ®->mr); in sdramc_initialize()
58 writel(AT91_SDRAMC_MODE_LMR, ®->mr); in sdramc_initialize()
66 writel(AT91_SDRAMC_MODE_NORMAL, ®->mr); in sdramc_initialize()
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| H A D | phy.c | 28 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; in at91_phy_reset()
37 AT91_RSTC_MR_URSTEN, &rstc->mr); in at91_phy_reset()
55 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); in at91_phy_reset()
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/ |
| H A D | emif-common.c | 57 u32 mr; in get_mr() local
63 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); in get_mr()
65 mr = readl(&emif->emif_lpddr2_mode_reg_data); in get_mr()
67 cs, mr_addr, mr); in get_mr()
68 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && in get_mr()
69 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && in get_mr()
70 ((mr & 0xff000000) >> 24) == (mr & 0xff)) in get_mr()
71 return mr & 0xff; in get_mr()
73 return mr; in get_mr()
1017 u32 mr = 0, temp; in is_lpddr2_sdram_present() local
[all …]
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 365 u16 mr[4] = { 0, }; in mctl_channel_init() local
463 mr[0] = DDR3_MR0_PPD_FAST_EXIT | DDR3_MR0_WR(tWR) | in mctl_channel_init()
465 mr[1] = DDR3_MR1_RTT120OHM; in mctl_channel_init()
466 mr[2] = DDR3_MR2_TWL(CWL); in mctl_channel_init()
467 mr[3] = 0; in mctl_channel_init()
486 writel(MCTL_INIT3_MR(mr[0]) | MCTL_INIT3_EMR(mr[1]), in mctl_channel_init()
488 writel(MCTL_INIT4_EMR2(mr[2]) | MCTL_INIT4_EMR3(mr[3]), in mctl_channel_init()
507 writel(MCTL_INIT3_MR(mr[1]) | MCTL_INIT3_EMR(mr[2]), in mctl_channel_init()
509 writel(MCTL_INIT4_EMR2(mr[3]), in mctl_channel_init()
635 writel(mr[0], &mctl_phy->mr0); in mctl_channel_init()
[all …]
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/am33xx/ |
| H A D | ddr.c | 41 u32 mr; in get_mr() local
46 mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data); in get_mr()
47 debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr); in get_mr()
48 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && in get_mr()
49 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && in get_mr()
50 ((mr & 0xff000000) >> 24) == (mr & 0xff)) in get_mr()
51 return mr & 0xff; in get_mr()
53 return mr; in get_mr()
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/omap3/ |
| H A D | sdrc.c | 41 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
114 writel(timings->mr, &sdrc_base->cs[cs].mr); in write_sdrc_timings()
189 timings.mr = readl(&sdrc_base->cs[CS0].mr); in do_sdrc_init()
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| /rk3399_rockchip-uboot/drivers/dma/ |
| H A D | fsl_dma.c | 74 out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS); in dma_check()
113 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT); in dmacpy()
117 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS); in dmacpy()
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr3_1333.c | 48 writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ in mctl_set_timing_params()
49 writel(0x40, &mctl_ctl->mr[1]); in mctl_set_timing_params()
50 writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ in mctl_set_timing_params()
51 writel(0x0, &mctl_ctl->mr[3]); in mctl_set_timing_params()
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| H A D | ddr2_v3s.c | 48 writel(0x263, &mctl_ctl->mr[0]); in mctl_set_timing_params()
49 writel(0x4, &mctl_ctl->mr[1]); in mctl_set_timing_params()
50 writel(0x0, &mctl_ctl->mr[2]); in mctl_set_timing_params()
51 writel(0x0, &mctl_ctl->mr[3]); in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 48 writel(0xc3, &mctl_ctl->mr[1]); /* nWR=8, BL8 */ in mctl_set_timing_params()
49 writel(0xa, &mctl_ctl->mr[2]); /* RL=12, WL=6 */ in mctl_set_timing_params()
50 writel(0x2, &mctl_ctl->mr[3]); /* 40 0hms PD/PU */ in mctl_set_timing_params()
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| /rk3399_rockchip-uboot/drivers/watchdog/ |
| H A D | at91sam9_wdt.c | 49 if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) { in at91_wdt_settimeout()
66 writel(reg, &wd->mr); in at91_wdt_settimeout()
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| /rk3399_rockchip-uboot/arch/sandbox/cpu/ |
| H A D | eth-raw-os.c | 33 struct packet_mreq mr; in _raw_packet_start() local
69 mr.mr_ifindex = device->sll_ifindex; in _raw_packet_start()
70 mr.mr_type = PACKET_MR_PROMISC; in _raw_packet_start()
72 &mr, sizeof(mr)); in _raw_packet_start()
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| /rk3399_rockchip-uboot/examples/api/ |
| H A D | glue.c | 117 static struct mem_region mr[UB_MAX_MR]; variable
125 si.mr = mr; in ub_get_sys_info()
127 memset(&mr, 0, sizeof(mr)); in ub_get_sys_info()
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| H A D | demo.c | 220 if (si->mr[i].flags == 0) in test_dump_si()
223 printf(" start\t= 0x%08lx\n", si->mr[i].start); in test_dump_si()
224 printf(" size\t= 0x%08lx\n", si->mr[i].size); in test_dump_si()
226 switch(si->mr[i].flags & 0x000F) { in test_dump_si()
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| /rk3399_rockchip-uboot/drivers/rtc/ |
| H A D | at91sam9_rtt.c | 60 writel(32768+AT91_RTT_RTTRST, &rtt->mr); in rtc_set()
75 writel(32768+AT91_RTT_RTTRST, &rtt->mr); in rtc_reset()
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| /rk3399_rockchip-uboot/arch/arm/mach-at91/include/mach/ |
| H A D | at91_mc.h | 32 u32 mr; /* 0x00 SDRAMC Mode Register */ member
64 u32 mr; /* 0x00 SDRAMC Mode Register */ member
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| H A D | at91_rtt.h | 17 u32 mr; /* Mode Register RW 0x00008000 */ member
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| H A D | at91_pit.h | 17 u32 mr; /* 0x00 Mode Register */ member
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| H A D | at91_wdt.h | 25 u32 mr; member
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| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xx/ |
| H A D | start.S | 323 mr r1, r3 /* Set new stack pointer */
324 mr r9, r4 /* Save copy of Global Data pointer */
325 mr r10, r5 /* Save copy of Destination Address */
328 mr r3, r5 /* Destination Address */
384 mr r4,r3
390 mr r4,r3
465 mr r3, r9 /* Global Data pointer */
466 mr r4, r10 /* Destination Address */
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| /rk3399_rockchip-uboot/arch/m68k/cpu/mcf532x/ |
| H A D | cpu.c | 130 out_be16(&wdp->mr, wdog_module / 8192); in watchdog_init()
132 out_be16(&wdp->mr, wdog_module / 4096); in watchdog_init()
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| /rk3399_rockchip-uboot/arch/powerpc/include/asm/ |
| H A D | fsl_dma.h | 16 uint mr; /* DMA mode register */ member
50 uint mr; /* DMA mode register */ member
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| /rk3399_rockchip-uboot/board/corscience/tricorder/ |
| H A D | tricorder.c | 195 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
202 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
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| /rk3399_rockchip-uboot/drivers/mmc/ |
| H A D | gen_atmel_mci.c | 97 u32 mr; local
129 mr = MMCI_BF(CLKDIV, clkdiv);
133 mr |= MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF);
140 mr |= MMCI_BF(CLKODD, clkodd);
142 mr |= MMCI_BF(BLKLEN, blklen);
144 writel(mr, &mci->mr);
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