1*af930827SMasahiro Yamada /* 2*af930827SMasahiro Yamada * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 3*af930827SMasahiro Yamada * 4*af930827SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 5*af930827SMasahiro Yamada */ 6*af930827SMasahiro Yamada 7*af930827SMasahiro Yamada #ifndef AT91_MC_H 8*af930827SMasahiro Yamada #define AT91_MC_H 9*af930827SMasahiro Yamada 10*af930827SMasahiro Yamada #define AT91_ASM_MC_EBI_CSA (ATMEL_BASE_MC + 0x60) 11*af930827SMasahiro Yamada #define AT91_ASM_MC_EBI_CFG (ATMEL_BASE_MC + 0x64) 12*af930827SMasahiro Yamada #define AT91_ASM_MC_SMC_CSR0 (ATMEL_BASE_MC + 0x70) 13*af930827SMasahiro Yamada #define AT91_ASM_MC_SDRAMC_MR (ATMEL_BASE_MC + 0x90) 14*af930827SMasahiro Yamada #define AT91_ASM_MC_SDRAMC_TR (ATMEL_BASE_MC + 0x94) 15*af930827SMasahiro Yamada #define AT91_ASM_MC_SDRAMC_CR (ATMEL_BASE_MC + 0x98) 16*af930827SMasahiro Yamada 17*af930827SMasahiro Yamada #ifndef __ASSEMBLY__ 18*af930827SMasahiro Yamada 19*af930827SMasahiro Yamada typedef struct at91_ebi { 20*af930827SMasahiro Yamada u32 csa; /* 0x00 Chip Select Assignment Register */ 21*af930827SMasahiro Yamada u32 cfgr; /* 0x04 Configuration Register */ 22*af930827SMasahiro Yamada u32 reserved[2]; 23*af930827SMasahiro Yamada } at91_ebi_t; 24*af930827SMasahiro Yamada 25*af930827SMasahiro Yamada #define AT91_EBI_CSA_CS0A 0x0001 26*af930827SMasahiro Yamada #define AT91_EBI_CSA_CS1A 0x0002 27*af930827SMasahiro Yamada 28*af930827SMasahiro Yamada #define AT91_EBI_CSA_CS3A 0x0008 29*af930827SMasahiro Yamada #define AT91_EBI_CSA_CS4A 0x0010 30*af930827SMasahiro Yamada 31*af930827SMasahiro Yamada typedef struct at91_sdramc { 32*af930827SMasahiro Yamada u32 mr; /* 0x00 SDRAMC Mode Register */ 33*af930827SMasahiro Yamada u32 tr; /* 0x04 SDRAMC Refresh Timer Register */ 34*af930827SMasahiro Yamada u32 cr; /* 0x08 SDRAMC Configuration Register */ 35*af930827SMasahiro Yamada u32 ssr; /* 0x0C SDRAMC Self Refresh Register */ 36*af930827SMasahiro Yamada u32 lpr; /* 0x10 SDRAMC Low Power Register */ 37*af930827SMasahiro Yamada u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */ 38*af930827SMasahiro Yamada u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */ 39*af930827SMasahiro Yamada u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ 40*af930827SMasahiro Yamada u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ 41*af930827SMasahiro Yamada u32 reserved[3]; 42*af930827SMasahiro Yamada } at91_sdramc_t; 43*af930827SMasahiro Yamada 44*af930827SMasahiro Yamada typedef struct at91_smc { 45*af930827SMasahiro Yamada u32 csr[8]; /* 0x00 SDRAMC Mode Register */ 46*af930827SMasahiro Yamada } at91_smc_t; 47*af930827SMasahiro Yamada 48*af930827SMasahiro Yamada #define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28) 49*af930827SMasahiro Yamada #define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24) 50*af930827SMasahiro Yamada #define AT91_SMC_CSR_ACSS_STANDARD 0x00000000 51*af930827SMasahiro Yamada #define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000 52*af930827SMasahiro Yamada #define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000 53*af930827SMasahiro Yamada #define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000 54*af930827SMasahiro Yamada #define AT91_SMC_CSR_DRP 0x00008000 55*af930827SMasahiro Yamada #define AT91_SMC_CSR_DBW_8 0x00004000 56*af930827SMasahiro Yamada #define AT91_SMC_CSR_DBW_16 0x00002000 57*af930827SMasahiro Yamada #define AT91_SMC_CSR_BAT_8 0x00000000 58*af930827SMasahiro Yamada #define AT91_SMC_CSR_BAT_16 0x00001000 59*af930827SMasahiro Yamada #define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8) 60*af930827SMasahiro Yamada #define AT91_SMC_CSR_WSEN 0x00000080 61*af930827SMasahiro Yamada #define AT91_SMC_CSR_NWS(x) (x & 0x7F) 62*af930827SMasahiro Yamada 63*af930827SMasahiro Yamada typedef struct at91_bfc { 64*af930827SMasahiro Yamada u32 mr; /* 0x00 SDRAMC Mode Register */ 65*af930827SMasahiro Yamada } at91_bfc_t; 66*af930827SMasahiro Yamada 67*af930827SMasahiro Yamada typedef struct at91_mc { 68*af930827SMasahiro Yamada u32 rcr; /* 0x00 MC Remap Control Register */ 69*af930827SMasahiro Yamada u32 asr; /* 0x04 MC Abort Status Register */ 70*af930827SMasahiro Yamada u32 aasr; /* 0x08 MC Abort Address Status Reg */ 71*af930827SMasahiro Yamada u32 mpr; /* 0x0C MC Master Priority Register */ 72*af930827SMasahiro Yamada u32 reserved1[20]; /* 0x10-0x5C */ 73*af930827SMasahiro Yamada at91_ebi_t ebi; /* 0x60 - 0x6C EBI */ 74*af930827SMasahiro Yamada at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */ 75*af930827SMasahiro Yamada at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */ 76*af930827SMasahiro Yamada at91_bfc_t bfc; /* 0xC0 BFC User Interface */ 77*af930827SMasahiro Yamada u32 reserved2[15]; 78*af930827SMasahiro Yamada } at91_mc_t; 79*af930827SMasahiro Yamada 80*af930827SMasahiro Yamada #endif 81*af930827SMasahiro Yamada #endif 82