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/rk3399_rockchip-uboot/arch/microblaze/cpu/
H A Dinterrupts.c39 microblaze_intc_t *intc; variable
53 mask = intc->ier; in enable_one_interrupt()
54 intc->ier = (mask | offset); in enable_one_interrupt()
57 intc->ier); in enable_one_interrupt()
58 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in enable_one_interrupt()
59 intc->iar, intc->mer); in enable_one_interrupt()
68 mask = intc->ier; in disable_one_interrupt()
69 intc->ier = (mask & ~offset); in disable_one_interrupt()
72 intc->ier); in disable_one_interrupt()
73 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in disable_one_interrupt()
[all …]
/rk3399_rockchip-uboot/arch/powerpc/include/asm/
H A Dxilinx_irq.h11 #define intc XPAR_INTC_0_BASEADDR macro
12 #define ISR (intc + (0 * 4)) /* Interrupt Status Register */
13 #define IPR (intc + (1 * 4)) /* Interrupt Pending Register */
14 #define IER (intc + (2 * 4)) /* Interrupt Enable Register */
15 #define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */
16 #define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */
17 #define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */
18 #define IVR (intc + (6 * 4)) /* Interrupt Vector Register */
19 #define MER (intc + (7 * 4)) /* Master Enable Register */
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dzynq-7000.dtsi52 interrupt-parent = <&intc>;
70 interrupt-parent = <&intc>;
77 interrupt-parent = <&intc>;
88 interrupt-parent = <&intc>;
100 interrupt-parent = <&intc>;
112 interrupt-parent = <&intc>;
121 interrupt-parent = <&intc>;
132 interrupt-parent = <&intc>;
139 intc: interrupt-controller@f8f01000 { label
184 interrupt-parent = <&intc>;
[all …]
H A Dbcm2836.dtsi12 compatible = "brcm,bcm2836-l1-intc";
73 &intc {
H A Dbcm2837.dtsi12 compatible = "brcm,bcm2836-l1-intc";
71 &intc {
H A Dlogicpd-torpedo-som.dtsi80 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
81 interrupt-parent = <&intc>;
111 interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
186 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
H A Domap3.dtsi17 interrupt-parent = <&intc>;
199 intc: interrupt-controller@48200000 { label
200 compatible = "ti,omap3-intc";
289 interrupts-extended = <&intc 72>;
299 interrupts-extended = <&intc 73>;
309 interrupts-extended = <&intc 74>;
715 interrupt-parent = <&intc>;
722 interrupt-parent = <&intc>;
833 interrupt-parent = <&intc>;
846 interrupt-parent = <&intc>;
H A Dlogicpd-som-lv.dtsi104 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
105 interrupt-parent = <&intc>;
123 interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
249 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
H A Dlogicpd-som-lv-37xx-devkit.dts163 interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
256 interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
H A Dtegra20.dtsi145 interrupt-parent = <&intc>;
152 intc: interrupt-controller@50041000 { label
158 interrupt-parent = <&intc>;
178 interrupt-parent = <&intc>;
596 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
H A Dbcm283x.dtsi14 interrupt-parent = <&intc>;
79 intc: interrupt-controller@7e00b200 { label
H A Ddm816x.dtsi12 interrupt-parent = <&intc>;
217 intc: interrupt-controller@48200000 { label
218 compatible = "ti,dm816-intc";
H A Dzynq-zturn-myir.dts158 interrupt-parent = <&intc>;
H A Dtegra30.dtsi26 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
231 interrupt-parent = <&intc>;
237 intc: interrupt-controller@50041000 { label
243 interrupt-parent = <&intc>;
264 interrupt-parent = <&intc>;
H A Dimx6qdl.dtsi167 interrupt-parent = <&intc>;
171 intc: interrupt-controller@00a01000 { label
177 interrupt-parent = <&intc>;
789 interrupt-parent = <&intc>;
987 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
988 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
H A Duniphier-sld8.dtsi52 interrupt-parent = <&intc>;
419 intc: interrupt-controller@60001000 { label
H A Duniphier-ld4.dtsi52 interrupt-parent = <&intc>;
419 intc: interrupt-controller@60001000 { label
H A Dlogicpd-torpedo-37xx-devkit.dts196 interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
398 interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
H A Dstih407-family.dtsi68 intc: interrupt-controller@08761000 { label
81 interrupt-parent = <&intc>;
98 interrupt-parent = <&intc>;
117 interrupt-parent = <&intc>;
/rk3399_rockchip-uboot/arch/nds32/dts/
H A Dag101p.dts6 interrupt-parent = <&intc>;
36 intc: interrupt-controller { label
H A Dae3xx.dts6 interrupt-parent = <&intc>;
36 intc: interrupt-controller { label
/rk3399_rockchip-uboot/doc/device-tree-bindings/i2c/
H A Di2c-cdns.txt18 interrupt-parent = <&intc>;
/rk3399_rockchip-uboot/doc/device-tree-bindings/spi/
H A Dspi-zynq-qspi.txt22 interrupt-parent = <&intc>;
H A Dspi-zynq.txt27 interrupt-parent = <&intc>;
/rk3399_rockchip-uboot/include/
H A Dtsi148.h103 unsigned int intc; /* 0x454 */ member

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