1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * (C) Copyright 2008 3*5b218ae1SRicardo Ribalda Delgado * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com 4a47a12beSStefan Roese * This work has been supported by: QTechnology http://qtec.com/ 5a47a12beSStefan Roese * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7a47a12beSStefan Roese */ 8a47a12beSStefan Roese #ifndef XILINX_IRQ_H 9a47a12beSStefan Roese #define XILINX_IRQ_H 10a47a12beSStefan Roese 11a47a12beSStefan Roese #define intc XPAR_INTC_0_BASEADDR 12a47a12beSStefan Roese #define ISR (intc + (0 * 4)) /* Interrupt Status Register */ 13a47a12beSStefan Roese #define IPR (intc + (1 * 4)) /* Interrupt Pending Register */ 14a47a12beSStefan Roese #define IER (intc + (2 * 4)) /* Interrupt Enable Register */ 15a47a12beSStefan Roese #define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */ 16a47a12beSStefan Roese #define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */ 17a47a12beSStefan Roese #define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */ 18a47a12beSStefan Roese #define IVR (intc + (6 * 4)) /* Interrupt Vector Register */ 19a47a12beSStefan Roese #define MER (intc + (7 * 4)) /* Master Enable Register */ 20a47a12beSStefan Roese 21a47a12beSStefan Roese #define IRQ_MASK(irq) (1 << (irq & 0x1f)) 22a47a12beSStefan Roese 23a47a12beSStefan Roese #define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS 24a47a12beSStefan Roese 25a47a12beSStefan Roese #endif 26