1*46025584SFabian Vogt#include "bcm283x.dtsi" 2*46025584SFabian Vogt 3*46025584SFabian Vogt/ { 4*46025584SFabian Vogt compatible = "brcm,bcm2836"; 5*46025584SFabian Vogt 6*46025584SFabian Vogt soc { 7*46025584SFabian Vogt ranges = <0x7e000000 0x3f000000 0x1000000>, 8*46025584SFabian Vogt <0x40000000 0x40000000 0x00001000>; 9*46025584SFabian Vogt dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 10*46025584SFabian Vogt 11*46025584SFabian Vogt local_intc: local_intc { 12*46025584SFabian Vogt compatible = "brcm,bcm2836-l1-intc"; 13*46025584SFabian Vogt reg = <0x40000000 0x100>; 14*46025584SFabian Vogt interrupt-controller; 15*46025584SFabian Vogt #interrupt-cells = <1>; 16*46025584SFabian Vogt interrupt-parent = <&local_intc>; 17*46025584SFabian Vogt }; 18*46025584SFabian Vogt 19*46025584SFabian Vogt arm-pmu { 20*46025584SFabian Vogt compatible = "arm,cortex-a7-pmu"; 21*46025584SFabian Vogt interrupt-parent = <&local_intc>; 22*46025584SFabian Vogt interrupts = <9>; 23*46025584SFabian Vogt }; 24*46025584SFabian Vogt }; 25*46025584SFabian Vogt 26*46025584SFabian Vogt timer { 27*46025584SFabian Vogt compatible = "arm,armv7-timer"; 28*46025584SFabian Vogt interrupt-parent = <&local_intc>; 29*46025584SFabian Vogt interrupts = <0>, // PHYS_SECURE_PPI 30*46025584SFabian Vogt <1>, // PHYS_NONSECURE_PPI 31*46025584SFabian Vogt <3>, // VIRT_PPI 32*46025584SFabian Vogt <2>; // HYP_PPI 33*46025584SFabian Vogt always-on; 34*46025584SFabian Vogt }; 35*46025584SFabian Vogt 36*46025584SFabian Vogt cpus: cpus { 37*46025584SFabian Vogt #address-cells = <1>; 38*46025584SFabian Vogt #size-cells = <0>; 39*46025584SFabian Vogt 40*46025584SFabian Vogt v7_cpu0: cpu@0 { 41*46025584SFabian Vogt device_type = "cpu"; 42*46025584SFabian Vogt compatible = "arm,cortex-a7"; 43*46025584SFabian Vogt reg = <0xf00>; 44*46025584SFabian Vogt clock-frequency = <800000000>; 45*46025584SFabian Vogt }; 46*46025584SFabian Vogt 47*46025584SFabian Vogt v7_cpu1: cpu@1 { 48*46025584SFabian Vogt device_type = "cpu"; 49*46025584SFabian Vogt compatible = "arm,cortex-a7"; 50*46025584SFabian Vogt reg = <0xf01>; 51*46025584SFabian Vogt clock-frequency = <800000000>; 52*46025584SFabian Vogt }; 53*46025584SFabian Vogt 54*46025584SFabian Vogt v7_cpu2: cpu@2 { 55*46025584SFabian Vogt device_type = "cpu"; 56*46025584SFabian Vogt compatible = "arm,cortex-a7"; 57*46025584SFabian Vogt reg = <0xf02>; 58*46025584SFabian Vogt clock-frequency = <800000000>; 59*46025584SFabian Vogt }; 60*46025584SFabian Vogt 61*46025584SFabian Vogt v7_cpu3: cpu@3 { 62*46025584SFabian Vogt device_type = "cpu"; 63*46025584SFabian Vogt compatible = "arm,cortex-a7"; 64*46025584SFabian Vogt reg = <0xf03>; 65*46025584SFabian Vogt clock-frequency = <800000000>; 66*46025584SFabian Vogt }; 67*46025584SFabian Vogt }; 68*46025584SFabian Vogt}; 69*46025584SFabian Vogt 70*46025584SFabian Vogt/* Make the BCM2835-style global interrupt controller be a child of the 71*46025584SFabian Vogt * CPU-local interrupt controller. 72*46025584SFabian Vogt */ 73*46025584SFabian Vogt&intc { 74*46025584SFabian Vogt compatible = "brcm,bcm2836-armctrl-ic"; 75*46025584SFabian Vogt reg = <0x7e00b200 0x200>; 76*46025584SFabian Vogt interrupt-parent = <&local_intc>; 77*46025584SFabian Vogt interrupts = <8>; 78*46025584SFabian Vogt}; 79