xref: /rk3399_rockchip-uboot/arch/nds32/dts/ag101p.dts (revision 8dc1b17f14c9201c7d0da0f33e404a7e051b2ec6)
186132af7Srick/dts-v1/;
286132af7Srick/ {
386132af7Srick	compatible = "nds32 ag101p";
486132af7Srick	#address-cells = <1>;
586132af7Srick	#size-cells = <1>;
686132af7Srick	interrupt-parent = <&intc>;
786132af7Srick
886132af7Srick	aliases {
986132af7Srick		uart0 = &serial0;
10*be71a179Srick		ethernet0 = &mac0;
1186132af7Srick	} ;
1286132af7Srick
1386132af7Srick	chosen {
1486132af7Srick		/* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */
1586132af7Srick		bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7";
1686132af7Srick		stdout-path = "uart0:38400n8";
17f5076f86Srick		tick-timer = &timer0;
1886132af7Srick	};
1986132af7Srick
2086132af7Srick	memory@0 {
2186132af7Srick		device_type = "memory";
2286132af7Srick		reg = <0x00000000 0x40000000>;
2386132af7Srick	};
2486132af7Srick
2586132af7Srick	cpus {
2686132af7Srick		#address-cells = <1>;
2786132af7Srick		#size-cells = <0>;
2886132af7Srick		cpu@0 {
2986132af7Srick			compatible = "andestech,n13";
3086132af7Srick			reg = <0>;
3186132af7Srick			/* FIXME: to fill correct frqeuency */
3286132af7Srick			clock-frequency = <60000000>;
3386132af7Srick		};
3486132af7Srick	};
3586132af7Srick
3686132af7Srick	intc: interrupt-controller {
3786132af7Srick		compatible = "andestech,atnointc010";
3886132af7Srick		#interrupt-cells = <1>;
3986132af7Srick		interrupt-controller;
4086132af7Srick	};
4186132af7Srick
4286132af7Srick	serial0: serial@99600000 {
4386132af7Srick		compatible = "andestech,uart16550", "ns16550a";
4486132af7Srick		reg = <0x99600000 0x1000>;
4586132af7Srick		interrupts = <7 4>;
4686132af7Srick		clock-frequency = <14745600>;
4786132af7Srick		reg-shift = <2>;
4886132af7Srick		no-loopback-test = <1>;
4986132af7Srick	};
5086132af7Srick
51f5076f86Srick	timer0: timer@98400000 {
52f5076f86Srick		compatible = "andestech,attmr010";
53f5076f86Srick		reg = <0x98400000 0x1000>;
54f5076f86Srick		interrupts = <19 4>;
55f5076f86Srick		clock-frequency = <15000000>;
56f5076f86Srick	};
57f5076f86Srick
58*be71a179Srick	mac0: mac@90900000 {
59*be71a179Srick		compatible = "andestech,atmac100";
60*be71a179Srick		reg = <0x90900000 0x1000>;
61*be71a179Srick		interrupts = <25 4>;
62*be71a179Srick	};
6386132af7Srick};
64