1*46025584SFabian Vogt#include "bcm283x.dtsi" 2*46025584SFabian Vogt 3*46025584SFabian Vogt/ { 4*46025584SFabian Vogt compatible = "brcm,bcm2836"; 5*46025584SFabian Vogt 6*46025584SFabian Vogt soc { 7*46025584SFabian Vogt ranges = <0x7e000000 0x3f000000 0x1000000>, 8*46025584SFabian Vogt <0x40000000 0x40000000 0x00001000>; 9*46025584SFabian Vogt dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 10*46025584SFabian Vogt 11*46025584SFabian Vogt local_intc: local_intc { 12*46025584SFabian Vogt compatible = "brcm,bcm2836-l1-intc"; 13*46025584SFabian Vogt reg = <0x40000000 0x100>; 14*46025584SFabian Vogt interrupt-controller; 15*46025584SFabian Vogt #interrupt-cells = <1>; 16*46025584SFabian Vogt interrupt-parent = <&local_intc>; 17*46025584SFabian Vogt }; 18*46025584SFabian Vogt }; 19*46025584SFabian Vogt 20*46025584SFabian Vogt timer { 21*46025584SFabian Vogt compatible = "arm,armv7-timer"; 22*46025584SFabian Vogt interrupt-parent = <&local_intc>; 23*46025584SFabian Vogt interrupts = <0>, // PHYS_SECURE_PPI 24*46025584SFabian Vogt <1>, // PHYS_NONSECURE_PPI 25*46025584SFabian Vogt <3>, // VIRT_PPI 26*46025584SFabian Vogt <2>; // HYP_PPI 27*46025584SFabian Vogt always-on; 28*46025584SFabian Vogt }; 29*46025584SFabian Vogt 30*46025584SFabian Vogt cpus: cpus { 31*46025584SFabian Vogt #address-cells = <1>; 32*46025584SFabian Vogt #size-cells = <0>; 33*46025584SFabian Vogt 34*46025584SFabian Vogt cpu0: cpu@0 { 35*46025584SFabian Vogt device_type = "cpu"; 36*46025584SFabian Vogt compatible = "arm,cortex-a53"; 37*46025584SFabian Vogt reg = <0>; 38*46025584SFabian Vogt enable-method = "spin-table"; 39*46025584SFabian Vogt cpu-release-addr = <0x0 0x000000d8>; 40*46025584SFabian Vogt }; 41*46025584SFabian Vogt 42*46025584SFabian Vogt cpu1: cpu@1 { 43*46025584SFabian Vogt device_type = "cpu"; 44*46025584SFabian Vogt compatible = "arm,cortex-a53"; 45*46025584SFabian Vogt reg = <1>; 46*46025584SFabian Vogt enable-method = "spin-table"; 47*46025584SFabian Vogt cpu-release-addr = <0x0 0x000000e0>; 48*46025584SFabian Vogt }; 49*46025584SFabian Vogt 50*46025584SFabian Vogt cpu2: cpu@2 { 51*46025584SFabian Vogt device_type = "cpu"; 52*46025584SFabian Vogt compatible = "arm,cortex-a53"; 53*46025584SFabian Vogt reg = <2>; 54*46025584SFabian Vogt enable-method = "spin-table"; 55*46025584SFabian Vogt cpu-release-addr = <0x0 0x000000e8>; 56*46025584SFabian Vogt }; 57*46025584SFabian Vogt 58*46025584SFabian Vogt cpu3: cpu@3 { 59*46025584SFabian Vogt device_type = "cpu"; 60*46025584SFabian Vogt compatible = "arm,cortex-a53"; 61*46025584SFabian Vogt reg = <3>; 62*46025584SFabian Vogt enable-method = "spin-table"; 63*46025584SFabian Vogt cpu-release-addr = <0x0 0x000000f0>; 64*46025584SFabian Vogt }; 65*46025584SFabian Vogt }; 66*46025584SFabian Vogt}; 67*46025584SFabian Vogt 68*46025584SFabian Vogt/* Make the BCM2835-style global interrupt controller be a child of the 69*46025584SFabian Vogt * CPU-local interrupt controller. 70*46025584SFabian Vogt */ 71*46025584SFabian Vogt&intc { 72*46025584SFabian Vogt compatible = "brcm,bcm2836-armctrl-ic"; 73*46025584SFabian Vogt reg = <0x7e00b200 0x200>; 74*46025584SFabian Vogt interrupt-parent = <&local_intc>; 75*46025584SFabian Vogt interrupts = <8>; 76*46025584SFabian Vogt}; 77