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Searched refs:hdmi (Results 1 – 25 of 104) sorted by relevance

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/rk3399_rockchip-uboot/drivers/video/
H A Ddw_hdmi.c56 static void hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset) in hdmi_write() argument
58 switch (hdmi->reg_io_width) { in hdmi_write()
60 writeb(val, hdmi->ioaddr + offset); in hdmi_write()
63 writel(val, hdmi->ioaddr + (offset << 2)); in hdmi_write()
71 static u8 hdmi_read(struct dw_hdmi *hdmi, int offset) in hdmi_read() argument
73 switch (hdmi->reg_io_width) { in hdmi_read()
75 return readb(hdmi->ioaddr + offset); in hdmi_read()
77 return readl(hdmi->ioaddr + (offset << 2)); in hdmi_read()
86 static void hdmi_mod(struct dw_hdmi *hdmi, unsigned reg, u8 mask, u8 data) in hdmi_mod() argument
88 u8 val = hdmi_read(hdmi, reg) & ~mask; in hdmi_mod()
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/rk3399_rockchip-uboot/drivers/video/drm/
H A Ddw_hdmi.c148 int (*configure)(struct dw_hdmi *hdmi,
206 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
207 u8 (*read)(struct dw_hdmi *hdmi, int offset);
215 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset) in dw_hdmi_writel() argument
217 writel(val, hdmi->regs + (offset << 2)); in dw_hdmi_writel()
220 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset) in dw_hdmi_readl() argument
222 return readl(hdmi->regs + (offset << 2)); in dw_hdmi_readl()
225 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) in dw_hdmi_writeb() argument
227 writeb(val, hdmi->regs + offset); in dw_hdmi_writeb()
230 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset) in dw_hdmi_readb() argument
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H A Ddw_hdmi_qp.c72 int (*configure)(struct dw_hdmi *hdmi,
120 void (*write)(struct dw_hdmi_qp *hdmi, u32 val, int offset);
121 u8 (*read)(struct dw_hdmi_qp *hdmi, int offset);
127 static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset) in hdmi_writel() argument
129 writel(val, hdmi->regs + offset); in hdmi_writel()
132 static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset) in hdmi_readl() argument
134 return readl(hdmi->regs + offset); in hdmi_readl()
138 hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, unsigned int reg) in hdmi_modb() argument
140 u32 val = hdmi_readl(hdmi, reg) & ~mask; in hdmi_modb()
143 hdmi_writel(hdmi, val, reg); in hdmi_modb()
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H A Dinno_hdmi.c175 static void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val) in hdmi_writeb() argument
177 writel(val, hdmi->regs + (offset << 2)); in hdmi_writeb()
180 static u32 hdmi_readb(struct inno_hdmi *hdmi, u16 offset) in hdmi_readb() argument
182 return readl(hdmi->regs + (offset << 2)); in hdmi_readb()
185 static void hdmi_modb(struct inno_hdmi *hdmi, u16 offset, u32 msk, u32 val) in hdmi_modb() argument
187 u32 temp = hdmi_readb(hdmi, offset) & ~msk; in hdmi_modb()
190 hdmi_writeb(hdmi, offset, temp); in hdmi_modb()
193 static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable) in inno_hdmi_sys_power() argument
196 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON); in inno_hdmi_sys_power()
198 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF); in inno_hdmi_sys_power()
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H A Drockchip_dw_hdmi_qp.c145 void (*set_link_mode)(struct rockchip_hdmi *hdmi);
146 void (*set_color_format)(struct rockchip_hdmi *hdmi, u64 bus_format, u32 depth);
147 void (*get_grf_color_fmt)(struct rockchip_hdmi *hdmi, u32 *fmt, u32 *depth);
148 void (*io_path_init)(struct rockchip_hdmi *hdmi);
149 enum drm_connector_status (*read_hpd)(struct rockchip_hdmi *hdmi);
502 hdmi_get_tmdsclock(struct rockchip_hdmi *hdmi, unsigned long pixelclock) in hdmi_get_tmdsclock() argument
506 hdmi_bus_fmt_color_depth(hdmi->output_bus_format); in hdmi_get_tmdsclock()
508 if (!hdmi_bus_fmt_is_yuv422(hdmi->output_bus_format)) { in hdmi_get_tmdsclock()
528 rockchip_hdmi_if_dsc_enable(struct rockchip_hdmi *hdmi, unsigned int tmdsclk) in rockchip_hdmi_if_dsc_enable() argument
531 u64 frl_rate = (u64)hdmi->link_cfg.frl_lanes * in rockchip_hdmi_if_dsc_enable()
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H A Drockchip_dw_hdmi.h22 inno_dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
28 void inno_dw_hdmi_mode_valid(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data);
H A DMakefile25 obj-$(CONFIG_ROCKCHIP_INNO_HDMI_PHY) += rockchip-inno-hdmi-phy.o
30 obj-$(CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI) += phy-rockchip-samsung-hdptx-hdmi.o
45 …nector.o rockchip_post_csc.o rockchip_vop2.o rockchip_phy.o rockchip-inno-hdmi-phy.o rockchip_dw_h…
/rk3399_rockchip-uboot/drivers/video/rockchip/
H A Drk_hdmi.c79 return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); in rk_hdmi_read_edid()
85 struct dw_hdmi *hdmi = &priv->hdmi; in rk_hdmi_ofdata_to_platdata() local
87 hdmi->ioaddr = (ulong)devfdt_get_addr(dev); in rk_hdmi_ofdata_to_platdata()
88 hdmi->mpll_cfg = rockchip_mpll_cfg; in rk_hdmi_ofdata_to_platdata()
89 hdmi->phy_cfg = rockchip_phy_config; in rk_hdmi_ofdata_to_platdata()
93 hdmi->reg_io_width = 4; in rk_hdmi_ofdata_to_platdata()
94 hdmi->phy_set = dw_hdmi_phy_cfg; in rk_hdmi_ofdata_to_platdata()
110 struct dw_hdmi *hdmi = &priv->hdmi; in rk_hdmi_probe() local
113 ret = dw_hdmi_phy_wait_for_hpd(hdmi); in rk_hdmi_probe()
119 dw_hdmi_init(hdmi); in rk_hdmi_probe()
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H A Drk3288_hdmi.c43 struct dw_hdmi *hdmi = &priv->hdmi; in rk3288_hdmi_ofdata_to_platdata() local
45 hdmi->i2c_clk_high = 0x7a; in rk3288_hdmi_ofdata_to_platdata()
46 hdmi->i2c_clk_low = 0x8d; in rk3288_hdmi_ofdata_to_platdata()
52 hdmi->i2c_clk_high = 0x0d; in rk3288_hdmi_ofdata_to_platdata()
53 hdmi->i2c_clk_low = 0x0d; in rk3288_hdmi_ofdata_to_platdata()
H A Drk3399_hdmi.c35 return dw_hdmi_enable(&priv->hdmi, edid); in rk3399_hdmi_enable()
41 struct dw_hdmi *hdmi = &priv->hdmi; in rk3399_hdmi_ofdata_to_platdata() local
43 hdmi->i2c_clk_high = 0x7a; in rk3399_hdmi_ofdata_to_platdata()
44 hdmi->i2c_clk_low = 0x8d; in rk3399_hdmi_ofdata_to_platdata()
H A DMakefile14 obj-hdmi-$(CONFIG_ROCKCHIP_RK3288) += rk3288_hdmi.o
15 obj-hdmi-$(CONFIG_ROCKCHIP_RK3399) += rk3399_hdmi.o
16 obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o $(obj-hdmi-y)
H A Drk_hdmi.h22 struct dw_hdmi hdmi; member
/rk3399_rockchip-uboot/include/linux/
H A Ddw_hdmi.h140 int (*init)(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data);
141 void (*disable)(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data);
142 enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi,
144 void (*mode_valid)(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data);
148 int (*init)(struct rockchip_connector *conn, void *hdmi, void *data);
149 void (*disable)(struct rockchip_connector *conn, void *hdmi, void *data);
151 void (*mode_valid)(void *hdmi, void *data);
152 void (*set_pll)(struct rockchip_connector *conn, void *hdmi, void *data);
177 void *hdmi; member
185 int (*configure_phy)(struct dw_hdmi *hdmi,
/rk3399_rockchip-uboot/drivers/video/sunxi/
H A Dsunxi_display.c92 struct sunxi_hdmi_reg * const hdmi = in sunxi_hdmi_hpd_detect() local
112 writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl); in sunxi_hdmi_hpd_detect()
113 writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0); in sunxi_hdmi_hpd_detect()
116 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT) in sunxi_hdmi_hpd_detect()
127 struct sunxi_hdmi_reg * const hdmi = in sunxi_hdmi_shutdown() local
130 clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE); in sunxi_hdmi_shutdown()
141 struct sunxi_hdmi_reg * const hdmi = in sunxi_hdmi_ddc_do_command() local
144 setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR); in sunxi_hdmi_ddc_do_command()
148 SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr); in sunxi_hdmi_ddc_do_command()
150 writel(n, &hdmi->ddc_byte_count); in sunxi_hdmi_ddc_do_command()
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H A Dsunxi_dw_hdmi.c19 struct dw_hdmi hdmi; member
278 static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) in sunxi_dw_hdmi_phy_cfg() argument
290 return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); in sunxi_dw_hdmi_read_edid()
301 ret = dw_hdmi_enable(&priv->hdmi, edid); in sunxi_dw_hdmi_enable()
362 priv->hdmi.ioaddr = SUNXI_HDMI_BASE; in sunxi_dw_hdmi_probe()
363 priv->hdmi.i2c_clk_high = 0xd8; in sunxi_dw_hdmi_probe()
364 priv->hdmi.i2c_clk_low = 0xfe; in sunxi_dw_hdmi_probe()
365 priv->hdmi.reg_io_width = 1; in sunxi_dw_hdmi_probe()
366 priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg; in sunxi_dw_hdmi_probe()
369 dw_hdmi_init(&priv->hdmi); in sunxi_dw_hdmi_probe()
/rk3399_rockchip-uboot/doc/
H A DREADME.video38 U-Boot supports hdmi and lcd output on Allwinner sunxi SoCs, lcd output
43 - monitor=[none|dvi|hdmi|lcd|vga|composite-*] - Select the video output to use
45 dvi/hdmi: Selects output over the hdmi connector with dvi resp. hdmi output
54 - hpd=[0|1] - Enable use of the hdmi HotPlug Detect feature
55 0: Disabled. Configure dvi/hdmi output even if no cable is detected
59 - hpd_delay=<int> - How long to wait for the hdmi HPD signal in milliseconds
76 For example to always use the hdmi connector, even if no cable is inserted,
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/
H A Dsoc.c637 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; in imx_enable_hdmi_phy() local
639 reg = readb(&hdmi->phy_conf0); in imx_enable_hdmi_phy()
641 writeb(reg, &hdmi->phy_conf0); in imx_enable_hdmi_phy()
644 writeb(reg, &hdmi->phy_conf0); in imx_enable_hdmi_phy()
647 writeb(reg, &hdmi->phy_conf0); in imx_enable_hdmi_phy()
648 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); in imx_enable_hdmi_phy()
654 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; in imx_setup_hdmi() local
663 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); in imx_setup_hdmi()
675 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) { in imx_setup_hdmi()
677 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz); in imx_setup_hdmi()
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/rk3399_rockchip-uboot/arch/arm/mach-imx/
H A Dcmd_hdmidet.c13 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; in do_hdmidet() local
14 return (readb(&hdmi->phy_stat0) & HDMI_DVI_STAT) ? 0 : 1; in do_hdmidet()
H A Dvideo.c63 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; in detect_hdmi() local
64 return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; in detect_hdmi()
/rk3399_rockchip-uboot/include/
H A Ddw_hdmi.h475 int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
478 int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock);
479 int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi);
480 void dw_hdmi_phy_init(struct dw_hdmi *hdmi);
482 int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid);
483 int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size);
484 void dw_hdmi_init(struct dw_hdmi *hdmi);
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dimx6q.dtsi160 ipu2_di0_hdmi: hdmi-endpoint {
182 ipu2_di1_hdmi: hdmi-endpoint {
212 &hdmi {
213 compatible = "fsl,imx6q-hdmi";
H A Dbcm2835-rpi-b.dts21 &hdmi {
H A Dbcm2835-rpi-a.dts26 &hdmi {
H A Dbcm2835-rpi-b-rev2.dts27 &hdmi {
H A Dbcm2835-rpi-a-plus.dts33 &hdmi {

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