92 	struct sunxi_hdmi_reg * const hdmi =  in sunxi_hdmi_hpd_detect()  local
112 	writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);  in sunxi_hdmi_hpd_detect()
113 	writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);  in sunxi_hdmi_hpd_detect()
116 		if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)  in sunxi_hdmi_hpd_detect()
127 	struct sunxi_hdmi_reg * const hdmi =  in sunxi_hdmi_shutdown()  local
130 	clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);  in sunxi_hdmi_shutdown()
141 	struct sunxi_hdmi_reg * const hdmi =  in sunxi_hdmi_ddc_do_command()  local
144 	setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);  in sunxi_hdmi_ddc_do_command()
148 	       SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);  in sunxi_hdmi_ddc_do_command()
150 	writel(n, &hdmi->ddc_byte_count);  in sunxi_hdmi_ddc_do_command()
151 	writel(cmnd, &hdmi->ddc_cmnd);  in sunxi_hdmi_ddc_do_command()
153 	writel(n << 16 | cmnd, &hdmi->ddc_cmnd);  in sunxi_hdmi_ddc_do_command()
155 	setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);  in sunxi_hdmi_ddc_do_command()
157 	return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);  in sunxi_hdmi_ddc_do_command()
162 	struct sunxi_hdmi_reg * const hdmi =  in sunxi_hdmi_ddc_read()  local
178 			*buf++ = readb(&hdmi->ddc_fifo_data);  in sunxi_hdmi_ddc_read()
211 	struct sunxi_hdmi_reg * const hdmi =  in sunxi_hdmi_edid_get_mode()  local
219 	       &hdmi->pad_ctrl1);  in sunxi_hdmi_edid_get_mode()
221 	       &hdmi->pll_ctrl);  in sunxi_hdmi_edid_get_mode()
222 	writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);  in sunxi_hdmi_edid_get_mode()
229 	       SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);  in sunxi_hdmi_edid_get_mode()
230 	if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))  in sunxi_hdmi_edid_get_mode()
233 	writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);  in sunxi_hdmi_edid_get_mode()
236 	       SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);  in sunxi_hdmi_edid_get_mode()
261 	clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);  in sunxi_hdmi_edid_get_mode()
809 	struct sunxi_hdmi_reg * const hdmi =  local
840 		writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
842 	writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
843 	writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
846 		writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
848 	writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
849 	writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
851 	setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
857 	struct sunxi_hdmi_reg * const hdmi =  local
862 	writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
868 	writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
871 	writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
872 	writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
873 	writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
874 	writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
875 	writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
878 	clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
881 		setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
885 	       &hdmi->video_size);
889 	writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
893 	writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
897 	writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
900 		setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
903 		setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
908 	struct sunxi_hdmi_reg * const hdmi =  local
912 	setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);