145 	void (*set_link_mode)(struct rockchip_hdmi *hdmi);
146 	void (*set_color_format)(struct rockchip_hdmi *hdmi, u64 bus_format, u32 depth);
147 	void (*get_grf_color_fmt)(struct rockchip_hdmi *hdmi, u32 *fmt, u32 *depth);
148 	void (*io_path_init)(struct rockchip_hdmi *hdmi);
149 	enum drm_connector_status (*read_hpd)(struct rockchip_hdmi *hdmi);
502 hdmi_get_tmdsclock(struct rockchip_hdmi *hdmi, unsigned long pixelclock)  in hdmi_get_tmdsclock()  argument
506 		hdmi_bus_fmt_color_depth(hdmi->output_bus_format);  in hdmi_get_tmdsclock()
508 	if (!hdmi_bus_fmt_is_yuv422(hdmi->output_bus_format)) {  in hdmi_get_tmdsclock()
528 rockchip_hdmi_if_dsc_enable(struct rockchip_hdmi *hdmi, unsigned int tmdsclk)  in rockchip_hdmi_if_dsc_enable()  argument
531 	u64 frl_rate = (u64)hdmi->link_cfg.frl_lanes *  in rockchip_hdmi_if_dsc_enable()
532 		hdmi->link_cfg.rate_per_lane * 1000000;  in rockchip_hdmi_if_dsc_enable()
533 	u8 bpp = hdmi_bus_fmt_color_depth(hdmi->bus_format) * 3;  in rockchip_hdmi_if_dsc_enable()
536 	if (hdmi_bus_fmt_is_yuv420(hdmi->bus_format) ||  in rockchip_hdmi_if_dsc_enable()
537 	    hdmi_bus_fmt_is_yuv422(hdmi->bus_format))  in rockchip_hdmi_if_dsc_enable()
549 static void hdmi_select_link_config(struct rockchip_hdmi *hdmi,  in hdmi_select_link_config()  argument
557 	max_lanes = hdmi->max_lanes;  in hdmi_select_link_config()
558 	max_rate_per_lane = hdmi->max_frl_rate_per_lane;  in hdmi_select_link_config()
561 	hdmi->link_cfg.dsc_mode = false;  in hdmi_select_link_config()
562 	hdmi->link_cfg.frl_lanes = max_lanes;  in hdmi_select_link_config()
563 	hdmi->link_cfg.rate_per_lane = max_rate_per_lane;  in hdmi_select_link_config()
564 	hdmi->link_cfg.allm_en = hdmi->allm_en;  in hdmi_select_link_config()
569 		hdmi->link_cfg.frl_mode = false;  in hdmi_select_link_config()
573 	hdmi->link_cfg.frl_mode = true;  in hdmi_select_link_config()
575 	if (!hdmi->dsc_cap.v_1p2)  in hdmi_select_link_config()
578 	max_dsc_lanes = hdmi->dsc_cap.max_lanes;  in hdmi_select_link_config()
580 		hdmi->dsc_cap.max_frl_rate_per_lane;  in hdmi_select_link_config()
582 	if (rockchip_hdmi_if_dsc_enable(hdmi, tmdsclk)) {  in hdmi_select_link_config()
583 		hdmi->link_cfg.dsc_mode = true;  in hdmi_select_link_config()
584 		hdmi->link_cfg.frl_lanes = max_dsc_lanes;  in hdmi_select_link_config()
585 		hdmi->link_cfg.rate_per_lane = max_dsc_rate_per_lane;  in hdmi_select_link_config()
587 		hdmi->link_cfg.dsc_mode = false;  in hdmi_select_link_config()
588 		hdmi->link_cfg.frl_lanes = max_lanes;  in hdmi_select_link_config()
589 		hdmi->link_cfg.rate_per_lane = max_rate_per_lane;  in hdmi_select_link_config()
613 static int hdmi_dsc_get_num_slices(struct rockchip_hdmi *hdmi,  in hdmi_dsc_get_num_slices()  argument
647 	if (hdmi_bus_fmt_is_yuv444(hdmi->output_bus_format) ||  in hdmi_dsc_get_num_slices()
648 	    hdmi_bus_fmt_is_rgb(hdmi->output_bus_format))  in hdmi_dsc_get_num_slices()
709 static int hdmi_dsc_slices(struct rockchip_hdmi *hdmi,  in hdmi_dsc_slices()  argument
712 	int hdmi_throughput = hdmi->dsc_cap.clk_per_slice;  in hdmi_dsc_slices()
713 	int hdmi_max_slices = hdmi->dsc_cap.max_slices;  in hdmi_dsc_slices()
717 	return hdmi_dsc_get_num_slices(hdmi, mode, rk_max_slices,  in hdmi_dsc_slices()
723 hdmi_dsc_get_bpp(struct rockchip_hdmi *hdmi, int src_fractional_bpp,  in hdmi_dsc_get_bpp()  argument
734 	u8 original_bpp = hdmi_bus_fmt_color_depth(hdmi->output_bus_format) * 3;  in hdmi_dsc_get_bpp()
737 		dev_err(hdmi->dev, "can't get original_bpp\n");  in hdmi_dsc_get_bpp()
777 	frl_rate = (u64)hdmi->link_cfg.frl_lanes *  in hdmi_dsc_get_bpp()
778 		hdmi->link_cfg.rate_per_lane * 1000000;  in hdmi_dsc_get_bpp()
813 dw_hdmi_dsc_bpp(struct rockchip_hdmi *hdmi,  in dw_hdmi_dsc_bpp()  argument
816 	bool hdmi_all_bpp = hdmi->dsc_cap.all_bpp;  in dw_hdmi_dsc_bpp()
818 	int hdmi_max_chunk_bytes = hdmi->dsc_cap.total_chunk_kbytes * 1024;  in dw_hdmi_dsc_bpp()
820 	return hdmi_dsc_get_bpp(hdmi, fractional_bpp, slice_width,  in dw_hdmi_dsc_bpp()
825 static int dw_hdmi_qp_set_link_cfg(struct rockchip_hdmi *hdmi,  in dw_hdmi_qp_set_link_cfg()  argument
842 		dev_err(hdmi->dev, "can't find pps cfg!\n");  in dw_hdmi_qp_set_link_cfg()
846 	memcpy(hdmi->link_cfg.pps_payload, pps_datas[i].raw_pps, 128);  in dw_hdmi_qp_set_link_cfg()
849 	if (hdmi_bus_fmt_is_rgb(hdmi->output_bus_format))  in dw_hdmi_qp_set_link_cfg()
850 		hdmi->link_cfg.pps_payload[4] |= BIT(4);  in dw_hdmi_qp_set_link_cfg()
852 		hdmi->link_cfg.pps_payload[4] &= ~BIT(4);  in dw_hdmi_qp_set_link_cfg()
854 	hdmi->link_cfg.hcactive = DIV_ROUND_UP(slice_width * (bits_per_pixel / 16), 8) *  in dw_hdmi_qp_set_link_cfg()
860 static void dw_hdmi_qp_dsc_configure(struct rockchip_hdmi *hdmi,  in dw_hdmi_qp_dsc_configure()  argument
870 	unsigned int depth = hdmi_bus_fmt_color_depth(hdmi->output_bus_format);  in dw_hdmi_qp_dsc_configure()
872 	hdmi_is_dsc_1_2 = hdmi->dsc_cap.v_1p2;  in dw_hdmi_qp_dsc_configure()
877 	if (hdmi_bus_fmt_is_yuv422(hdmi->output_bus_format) ||  in dw_hdmi_qp_dsc_configure()
878 	    hdmi_bus_fmt_is_yuv420(hdmi->output_bus_format)) {  in dw_hdmi_qp_dsc_configure()
879 		dev_err(hdmi->dev, "dsc can't support yuv422/420\n");  in dw_hdmi_qp_dsc_configure()
887 	slice_count = hdmi_dsc_slices(hdmi, mode);  in dw_hdmi_qp_dsc_configure()
894 		dw_hdmi_dsc_bpp(hdmi, slice_count, slice_width, mode->clock);  in dw_hdmi_qp_dsc_configure()
898 	ret = dw_hdmi_qp_set_link_cfg(hdmi, mode->hdisplay,  in dw_hdmi_qp_dsc_configure()
903 		dev_err(hdmi->dev, "set vdsc cfg failed\n");  in dw_hdmi_qp_dsc_configure()
917 	memcpy(&s->pps, hdmi->link_cfg.pps_payload, 128);  in dw_hdmi_qp_dsc_configure()
920 static unsigned int drm_rk_select_color(struct rockchip_hdmi *hdmi,  in drm_rk_select_color()  argument
928 	struct drm_hdmi_info *hdmi_info = &edid_data->display_info.hdmi;  in drm_rk_select_color()
987 	    info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)  in drm_rk_select_color()
999 	      hdmi->force_disable_dsc)))  in drm_rk_select_color()
1067 	struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;  in dw_hdmi_qp_select_output()  local
1068 	struct drm_hdmi_info *hdmi_info = &edid_data->display_info.hdmi;  in dw_hdmi_qp_select_output()
1092 	hdmi->max_frl_rate_per_lane = hdmi_info->max_frl_rate_per_lane;  in dw_hdmi_qp_select_output()
1093 	hdmi->max_lanes = hdmi_info->max_lanes;  in dw_hdmi_qp_select_output()
1094 	memcpy(&hdmi->dsc_cap, &hdmi_info->dsc_cap, sizeof(struct drm_hdmi_dsc_cap));  in dw_hdmi_qp_select_output()
1170 			hdmi->allm_en = true;  in dw_hdmi_qp_select_output()
1172 			hdmi->allm_en = false;  in dw_hdmi_qp_select_output()
1203 	*bus_format = drm_rk_select_color(hdmi, edid_data, screen_info,  in dw_hdmi_qp_select_output()
1206 	hdmi->output_bus_format = *bus_format;  in dw_hdmi_qp_select_output()
1214 	hdmi->bus_format = *bus_format;  in dw_hdmi_qp_select_output()
1217 	tmdsclk = hdmi_get_tmdsclock(hdmi, pixel_clk);  in dw_hdmi_qp_select_output()
1218 	if (hdmi_bus_fmt_is_yuv420(hdmi->output_bus_format))  in dw_hdmi_qp_select_output()
1220 	hdmi_select_link_config(hdmi, edid_data->preferred_mode, tmdsclk);  in dw_hdmi_qp_select_output()
1223 	if (hdmi->link_cfg.dsc_mode)  in dw_hdmi_qp_select_output()
1224 		dw_hdmi_qp_dsc_configure(hdmi, s, edid_data->preferred_mode);  in dw_hdmi_qp_select_output()
1225 	if (hdmi->link_cfg.frl_mode) {  in dw_hdmi_qp_select_output()
1226 		if (dm_gpio_is_valid(&hdmi->enable_gpio))  in dw_hdmi_qp_select_output()
1227 			dm_gpio_set_value(&hdmi->enable_gpio, 0);  in dw_hdmi_qp_select_output()
1229 		if (hdmi->link_cfg.rate_per_lane >= 10) {  in dw_hdmi_qp_select_output()
1230 			hdmi->link_cfg.frl_lanes = 4;  in dw_hdmi_qp_select_output()
1231 			hdmi->link_cfg.rate_per_lane = 10;  in dw_hdmi_qp_select_output()
1233 		hdmi->bus_width = hdmi->link_cfg.frl_lanes *  in dw_hdmi_qp_select_output()
1234 			hdmi->link_cfg.rate_per_lane * 1000000;  in dw_hdmi_qp_select_output()
1237 			hdmi->bus_width |=  in dw_hdmi_qp_select_output()
1240 			hdmi->bus_width |= HDMI_FRL_MODE;  in dw_hdmi_qp_select_output()
1242 		if (dm_gpio_is_valid(&hdmi->enable_gpio))  in dw_hdmi_qp_select_output()
1243 			dm_gpio_set_value(&hdmi->enable_gpio, 1);  in dw_hdmi_qp_select_output()
1244 		hdmi->bus_width =  in dw_hdmi_qp_select_output()
1245 			hdmi_get_tmdsclock(hdmi, pixel_clk * 10);  in dw_hdmi_qp_select_output()
1247 			hdmi->bus_width /= 2;  in dw_hdmi_qp_select_output()
1250 			hdmi->bus_width |= COLOR_DEPTH_10BIT;  in dw_hdmi_qp_select_output()
1253 	rockchip_phy_set_bus_width(conn->phy, hdmi->bus_width);  in dw_hdmi_qp_select_output()
1258 	struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;  in dw_hdmi_qp_check_enable_gpio()  local
1260 	if (!hdmi->enable_gpio.dev)  in dw_hdmi_qp_check_enable_gpio()
1266 static void rk3576_set_link_mode(struct rockchip_hdmi *hdmi)  in rk3576_set_link_mode()  argument
1270 	if (!hdmi->link_cfg.frl_mode)  in rk3576_set_link_mode()
1274 	writel(val, hdmi->vo0_grf + RK3576_VO0_GRF_SOC_CON1);  in rk3576_set_link_mode()
1277 static void rk3588_set_link_mode(struct rockchip_hdmi *hdmi)  in rk3588_set_link_mode()  argument
1282 	if (!hdmi->id)  in rk3588_set_link_mode()
1287 	if (!hdmi->link_cfg.frl_mode) {  in rk3588_set_link_mode()
1290 			writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON4);  in rk3588_set_link_mode()
1292 			writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON7);  in rk3588_set_link_mode()
1296 			writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON3);  in rk3588_set_link_mode()
1298 			writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON6);  in rk3588_set_link_mode()
1305 		writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON4);  in rk3588_set_link_mode()
1307 		writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON7);  in rk3588_set_link_mode()
1309 	if (hdmi->link_cfg.dsc_mode) {  in rk3588_set_link_mode()
1313 			writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON3);  in rk3588_set_link_mode()
1315 			writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON6);  in rk3588_set_link_mode()
1319 			writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON3);  in rk3588_set_link_mode()
1321 			writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON6);  in rk3588_set_link_mode()
1325 static void rk3576_set_color_format(struct rockchip_hdmi *hdmi, u64 bus_format,  in rk3576_set_color_format()  argument
1357 	writel(val, hdmi->vo0_grf + RK3576_VO0_GRF_SOC_CON8);  in rk3576_set_color_format()
1360 static void rk3588_set_color_format(struct rockchip_hdmi *hdmi, u64 bus_format,  in rk3588_set_color_format()  argument
1383 		dev_err(hdmi->dev, "can't set correct color format\n");  in rk3588_set_color_format()
1387 	if (hdmi->link_cfg.dsc_mode)  in rk3588_set_color_format()
1395 	if (!hdmi->id)  in rk3588_set_color_format()
1396 		writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON3);  in rk3588_set_color_format()
1398 		writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON6);  in rk3588_set_color_format()
1403 	struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;  in dw_hdmi_qp_set_grf_cfg()  local
1406 	hdmi->ops->set_link_mode(hdmi);  in dw_hdmi_qp_set_grf_cfg()
1407 	color_depth = hdmi_bus_fmt_color_depth(hdmi->bus_format);  in dw_hdmi_qp_set_grf_cfg()
1408 	hdmi->ops->set_color_format(hdmi, hdmi->bus_format, color_depth);  in dw_hdmi_qp_set_grf_cfg()
1412 void dw_hdmi_qp_rockchip_sda_delay_cal(struct rockchip_hdmi *hdmi, u8 *sda_dlyn, u8 *sda_div)  in dw_hdmi_qp_rockchip_sda_delay_cal()  argument
1418 		val = DIV_ROUND_UP(hdmi->sda_falling_delay_ns, (i + 1) * 40);  in dw_hdmi_qp_rockchip_sda_delay_cal()
1425 		dev_err(hdmi->dev, "delay %d ns,can't calculate correct sda falling delay cfg\n",  in dw_hdmi_qp_rockchip_sda_delay_cal()
1426 			hdmi->sda_falling_delay_ns);  in dw_hdmi_qp_rockchip_sda_delay_cal()
1434 static void rk3576_io_path_init(struct rockchip_hdmi *hdmi)  in rk3576_io_path_init()  argument
1443 	writel(val, hdmi->vo0_grf + RK3576_VO0_GRF_SOC_CON14);  in rk3576_io_path_init()
1446 	writel(val, hdmi->grf + RK3576_IOC_MISC_CON0);  in rk3576_io_path_init()
1448 	if (hdmi->sda_falling_delay_ns) {  in rk3576_io_path_init()
1449 		dw_hdmi_qp_rockchip_sda_delay_cal(hdmi, &sda_dlyn, &sda_div);  in rk3576_io_path_init()
1455 			writel(val, hdmi->vo0_grf + RK3576_VO0_GRF_SOC_CON12);  in rk3576_io_path_init()
1460 static void rk3588_io_path_init(struct rockchip_hdmi *hdmi)  in rk3588_io_path_init()  argument
1464 	if (!hdmi->id) {  in rk3588_io_path_init()
1469 		writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON3);  in rk3588_io_path_init()
1473 		writel(val, hdmi->grf + RK3588_GRF_SOC_CON7);  in rk3588_io_path_init()
1477 		writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON9);  in rk3588_io_path_init()
1483 		writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON6);  in rk3588_io_path_init()
1487 		writel(val, hdmi->grf + RK3588_GRF_SOC_CON7);  in rk3588_io_path_init()
1491 		writel(val, hdmi->vo1_grf + RK3588_GRF_VO1_CON9);  in rk3588_io_path_init()
1497 	struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;  in dw_hdmi_qp_io_path_init()  local
1499 	hdmi->ops->io_path_init(hdmi);  in dw_hdmi_qp_io_path_init()
1504 	struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;  in dw_hdmi_rockchip_get_link_cfg()  local
1506 	return &hdmi->link_cfg;  in dw_hdmi_rockchip_get_link_cfg()
1517 	struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;  in dw_hdmi_qp_rockchip_genphy_init()  local
1521 	rockchip_phy_set_bus_width(conn->phy, hdmi->bus_width);  in dw_hdmi_qp_rockchip_genphy_init()
1526 static enum drm_connector_status rk3576_read_hpd(struct rockchip_hdmi *hdmi)  in rk3576_read_hpd()  argument
1531 	val = readl(hdmi->grf + RK3576_IOC_HDMITX_HPD_STATUS);  in rk3576_read_hpd()
1541 static enum drm_connector_status rk3588_read_hpd(struct rockchip_hdmi *hdmi)  in rk3588_read_hpd()  argument
1546 	val = readl(hdmi->grf + RK3588_GRF_SOC_STATUS1);  in rk3588_read_hpd()
1548 	if (!hdmi->id) {  in rk3588_read_hpd()
1565 	struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;  in rockchip_hdmi_qp_read_hpd()  local
1567 	return hdmi->ops->read_hpd(hdmi);  in rockchip_hdmi_qp_read_hpd()
1572 	struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;  in rockchip_hdmi_qp_set_pll()  local
1573 	u32 rate = (hdmi->bus_width & DATA_RATE_MASK) * 100;  in rockchip_hdmi_qp_set_pll()
1575 	clk_set_rate(&hdmi->link_clk, rate);  in rockchip_hdmi_qp_set_pll()
1629 	struct rockchip_hdmi *hdmi = dev_get_priv(dev);  in rockchip_dw_hdmi_qp_probe()  local
1632 	hdmi->dev = dev;  in rockchip_dw_hdmi_qp_probe()
1633 	hdmi->plat_data = (const struct dw_hdmi_plat_data *)dev_get_driver_data(dev);  in rockchip_dw_hdmi_qp_probe()
1635 	hdmi->id = of_alias_get_id(ofnode_to_np(dev->node), "hdmi");  in rockchip_dw_hdmi_qp_probe()
1636 	if (hdmi->id < 0)  in rockchip_dw_hdmi_qp_probe()
1637 		hdmi->id = 0;  in rockchip_dw_hdmi_qp_probe()
1640 	hdmi->grf = regmap_get_range(map, 0);  in rockchip_dw_hdmi_qp_probe()
1642 	if (hdmi->grf <= 0) {  in rockchip_dw_hdmi_qp_probe()
1644 			__func__, hdmi->grf);  in rockchip_dw_hdmi_qp_probe()
1648 	if (hdmi->plat_data->dev_type == RK3588_HDMI) {  in rockchip_dw_hdmi_qp_probe()
1650 		hdmi->vo1_grf = regmap_get_range(map, 0);  in rockchip_dw_hdmi_qp_probe()
1652 		if (hdmi->vo1_grf <= 0) {  in rockchip_dw_hdmi_qp_probe()
1654 				__func__, hdmi->vo1_grf);  in rockchip_dw_hdmi_qp_probe()
1657 	} else if (hdmi->plat_data->dev_type == RK3576_HDMI) {  in rockchip_dw_hdmi_qp_probe()
1659 		hdmi->vo0_grf = regmap_get_range(map, 0);  in rockchip_dw_hdmi_qp_probe()
1661 		if (hdmi->vo0_grf <= 0) {  in rockchip_dw_hdmi_qp_probe()
1663 				__func__, hdmi->vo0_grf);  in rockchip_dw_hdmi_qp_probe()
1668 	hdmi->sda_falling_delay_ns =  in rockchip_dw_hdmi_qp_probe()
1672 				   &hdmi->enable_gpio, GPIOD_IS_OUT);  in rockchip_dw_hdmi_qp_probe()
1678 	ret = clk_get_by_name(dev, "link_clk", &hdmi->link_clk);  in rockchip_dw_hdmi_qp_probe()
1684 	hdmi->force_disable_dsc =  in rockchip_dw_hdmi_qp_probe()
1687 	hdmi->ops = (struct rockchip_hdmi_chip_ops *)hdmi->plat_data->chip_ops;  in rockchip_dw_hdmi_qp_probe()
1689 	rockchip_connector_bind(&hdmi->connector, dev, hdmi->id, &rockchip_dw_hdmi_qp_funcs,  in rockchip_dw_hdmi_qp_probe()