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/rk3399_rockchip-uboot/board/compulab/cl-som-am57x/
H A Dspl.c180 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
181 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
182 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
183 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
184 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
185 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
186 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
187 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
188 .gpu.pmic = &tps659038,
/rk3399_rockchip-uboot/board/ti/am57xx/
H A Dboard.c271 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
272 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
273 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
274 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
275 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
276 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
277 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
278 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
279 .gpu.pmic = &tps659038,
280 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
[all …]
/rk3399_rockchip-uboot/board/ti/dra7xx/
H A Devm.c330 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
331 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
332 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
333 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
334 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
335 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
336 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
337 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
338 .gpu.pmic = &tps659038,
339 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dimx6dl.dtsi108 gpu-subsystem {
109 compatible = "fsl,imx-gpu-subsystem";
H A Dimx6q.dtsi121 gpu_vg: gpu@02204000 {
206 gpu-subsystem {
207 compatible = "fsl,imx-gpu-subsystem";
H A Dstih410.dtsi391 clock-names = "gpu-clk";
393 reset-names = "gpu";
438 clock-names = "gpu-clk";
440 reset-names = "gpu";
H A Dzynqmp-zc1751-xm018-dc4.dts184 &gpu {
H A Dtegra20-paz00.dts124 gpu {
125 nvidia,pins = "gpu", "sdb", "sdd";
220 "gpu", "gpu7", "gpv", "i2cp", "pta",
H A Dimx7ulp.dtsi573 gpu: gpu@41800000 { label
574 compatible = "fsl,imx6q-gpu";
H A Dtegra20-ventana.dts138 gpu {
139 nvidia,pins = "gpu";
230 "gme", "gpu", "gpu7", "i2cp", "irrx",
H A Dzynqmp-zc1751-xm015-dc1.dts99 &gpu {
H A Dtegra20-tamonten.dtsi40 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
194 "dtc", "dte", "dtf", "gpu", "sdio1",
H A Dsun6i-a31s-sina31s-core.dtsi112 regulator-name = "vdd-gpu";
H A Ddra71-evm.dts57 /* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */
H A Dimx6sx.dtsi162 gpu: gpu@01800000 { label
1294 gpu-subsystem {
1295 compatible = "fsl,imx-gpu-subsystem";
1296 cores = <&gpu>;
H A Dsun6i-reference-design-tablet.dtsi137 regulator-name = "vdd-gpu";
H A Dsun6i-a31s-yones-toptech-bs1078-v2.dts156 regulator-name = "vdd-gpu";
H A Dtegra124.dtsi179 gpu@57000000 {
188 clock-names = "gpu", "pwr";
190 reset-names = "gpu";
1043 gpu {
H A Dtegra210.dtsi288 gpu@57000000 {
298 clock-names = "gpu", "pwr", "ref";
300 reset-names = "gpu";
H A Dtegra20-seaboard.dts148 gpu {
149 nvidia,pins = "gpu";
240 "gme", "gpu", "gpu7", "i2cp", "irrx",
H A Dbcm283x.dtsi301 vc4: gpu {
H A Dsun6i-a31-m9.dts182 regulator-name = "vdd-gpu";
H A Dsun6i-a31s-primo81.dts198 regulator-name = "vdd-gpu";
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A DMakefile30 obj-$(CONFIG_TEGRA_GPU) += gpu.o
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Dclocks-common.c623 debug("gpu: %d\n", vcores->gpu.value[opp]); in scale_vcores()
624 do_scale_vcore(vcores->gpu.addr, vcores->gpu.value[opp], in scale_vcores()
625 vcores->gpu.pmic); in scale_vcores()
627 abb_setup(vcores->gpu.efuse.reg[opp], in scale_vcores()
632 vcores->gpu.abb_tx_done_mask, in scale_vcores()

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