xref: /rk3399_rockchip-uboot/arch/arm/dts/tegra20-ventana.dts (revision 40e1236afeeacdadfa3865f70fc7e3b8016acbe2)
15ab502cbSMasahiro Yamada/dts-v1/;
25ab502cbSMasahiro Yamada
3ce02a71cSSimon Glass#include <dt-bindings/input/input.h>
45ab502cbSMasahiro Yamada#include "tegra20.dtsi"
55ab502cbSMasahiro Yamada
65ab502cbSMasahiro Yamada/ {
75ab502cbSMasahiro Yamada	model = "NVIDIA Tegra20 Ventana evaluation board";
85ab502cbSMasahiro Yamada	compatible = "nvidia,ventana", "nvidia,tegra20";
95ab502cbSMasahiro Yamada
10c3691392SSimon Glass	chosen {
11c3691392SSimon Glass		stdout-path = &uartd;
12c3691392SSimon Glass	};
13c3691392SSimon Glass
145ab502cbSMasahiro Yamada	aliases {
15ce02a71cSSimon Glass		rtc0 = "/i2c@7000d000/tps6586x@34";
16ce02a71cSSimon Glass		rtc1 = "/rtc@7000e000";
17ce02a71cSSimon Glass		serial0 = &uartd;
18*002ddbffSStephen Warren		usb0 = "/usb@c5000000";
19*002ddbffSStephen Warren		usb1 = "/usb@c5004000";
20*002ddbffSStephen Warren		usb2 = "/usb@c5008000";
2167748a73SStephen Warren		mmc0 = "/sdhci@c8000600";
2267748a73SStephen Warren		mmc1 = "/sdhci@c8000400";
235ab502cbSMasahiro Yamada	};
245ab502cbSMasahiro Yamada
255ab502cbSMasahiro Yamada	memory {
265ab502cbSMasahiro Yamada		reg = <0x00000000 0x40000000>;
275ab502cbSMasahiro Yamada	};
285ab502cbSMasahiro Yamada
29ee7d755aSSimon Glass	host1x@50000000 {
305ab502cbSMasahiro Yamada		status = "okay";
315ab502cbSMasahiro Yamada		dc@54200000 {
325ab502cbSMasahiro Yamada			status = "okay";
335ab502cbSMasahiro Yamada			rgb {
345ab502cbSMasahiro Yamada				status = "okay";
35ec550770SSimon Glass
36ec550770SSimon Glass				nvidia,panel = <&panel>;
37ec550770SSimon Glass
38ec550770SSimon Glass				display-timings {
39ec550770SSimon Glass					timing@0 {
40ec550770SSimon Glass						/* Seaboard has 1366x768 */
41ec550770SSimon Glass						clock-frequency = <70600000>;
42ec550770SSimon Glass						hactive = <1366>;
43ec550770SSimon Glass						vactive = <768>;
44ec550770SSimon Glass						hback-porch = <58>;
45ec550770SSimon Glass						hfront-porch = <58>;
46ec550770SSimon Glass						hsync-len = <58>;
47ec550770SSimon Glass						vback-porch = <4>;
48ec550770SSimon Glass						vfront-porch = <4>;
49ec550770SSimon Glass						vsync-len = <4>;
50ec550770SSimon Glass						hsync-active = <1>;
51ec550770SSimon Glass					};
52ec550770SSimon Glass				};
535ab502cbSMasahiro Yamada			};
545ab502cbSMasahiro Yamada		};
55ce02a71cSSimon Glass
56ce02a71cSSimon Glass		hdmi@54280000 {
57ce02a71cSSimon Glass			status = "okay";
58ce02a71cSSimon Glass
59ce02a71cSSimon Glass			vdd-supply = <&hdmi_vdd_reg>;
60ce02a71cSSimon Glass			pll-supply = <&hdmi_pll_reg>;
61ce02a71cSSimon Glass
62ce02a71cSSimon Glass			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
63ce02a71cSSimon Glass			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
64ce02a71cSSimon Glass				GPIO_ACTIVE_HIGH>;
65ce02a71cSSimon Glass		};
66ce02a71cSSimon Glass	};
67ce02a71cSSimon Glass
68ce02a71cSSimon Glass	pinmux@70000014 {
69ce02a71cSSimon Glass		pinctrl-names = "default";
70ce02a71cSSimon Glass		pinctrl-0 = <&state_default>;
71ce02a71cSSimon Glass
72ce02a71cSSimon Glass		state_default: pinmux {
73ce02a71cSSimon Glass			ata {
74ce02a71cSSimon Glass				nvidia,pins = "ata";
75ce02a71cSSimon Glass				nvidia,function = "ide";
76ce02a71cSSimon Glass			};
77ce02a71cSSimon Glass			atb {
78ce02a71cSSimon Glass				nvidia,pins = "atb", "gma", "gme";
79ce02a71cSSimon Glass				nvidia,function = "sdio4";
80ce02a71cSSimon Glass			};
81ce02a71cSSimon Glass			atc {
82ce02a71cSSimon Glass				nvidia,pins = "atc";
83ce02a71cSSimon Glass				nvidia,function = "nand";
84ce02a71cSSimon Glass			};
85ce02a71cSSimon Glass			atd {
86ce02a71cSSimon Glass				nvidia,pins = "atd", "ate", "gmb", "spia",
87ce02a71cSSimon Glass					"spib", "spic";
88ce02a71cSSimon Glass				nvidia,function = "gmi";
89ce02a71cSSimon Glass			};
90ce02a71cSSimon Glass			cdev1 {
91ce02a71cSSimon Glass				nvidia,pins = "cdev1";
92ce02a71cSSimon Glass				nvidia,function = "plla_out";
93ce02a71cSSimon Glass			};
94ce02a71cSSimon Glass			cdev2 {
95ce02a71cSSimon Glass				nvidia,pins = "cdev2";
96ce02a71cSSimon Glass				nvidia,function = "pllp_out4";
97ce02a71cSSimon Glass			};
98ce02a71cSSimon Glass			crtp {
99ce02a71cSSimon Glass				nvidia,pins = "crtp", "lm1";
100ce02a71cSSimon Glass				nvidia,function = "crt";
101ce02a71cSSimon Glass			};
102ce02a71cSSimon Glass			csus {
103ce02a71cSSimon Glass				nvidia,pins = "csus";
104ce02a71cSSimon Glass				nvidia,function = "vi_sensor_clk";
105ce02a71cSSimon Glass			};
106ce02a71cSSimon Glass			dap1 {
107ce02a71cSSimon Glass				nvidia,pins = "dap1";
108ce02a71cSSimon Glass				nvidia,function = "dap1";
109ce02a71cSSimon Glass			};
110ce02a71cSSimon Glass			dap2 {
111ce02a71cSSimon Glass				nvidia,pins = "dap2";
112ce02a71cSSimon Glass				nvidia,function = "dap2";
113ce02a71cSSimon Glass			};
114ce02a71cSSimon Glass			dap3 {
115ce02a71cSSimon Glass				nvidia,pins = "dap3";
116ce02a71cSSimon Glass				nvidia,function = "dap3";
117ce02a71cSSimon Glass			};
118ce02a71cSSimon Glass			dap4 {
119ce02a71cSSimon Glass				nvidia,pins = "dap4";
120ce02a71cSSimon Glass				nvidia,function = "dap4";
121ce02a71cSSimon Glass			};
122ce02a71cSSimon Glass			dta {
123ce02a71cSSimon Glass				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
124ce02a71cSSimon Glass				nvidia,function = "vi";
125ce02a71cSSimon Glass			};
126ce02a71cSSimon Glass			dtf {
127ce02a71cSSimon Glass				nvidia,pins = "dtf";
128ce02a71cSSimon Glass				nvidia,function = "i2c3";
129ce02a71cSSimon Glass			};
130ce02a71cSSimon Glass			gmc {
131ce02a71cSSimon Glass				nvidia,pins = "gmc";
132ce02a71cSSimon Glass				nvidia,function = "uartd";
133ce02a71cSSimon Glass			};
134ce02a71cSSimon Glass			gmd {
135ce02a71cSSimon Glass				nvidia,pins = "gmd";
136ce02a71cSSimon Glass				nvidia,function = "sflash";
137ce02a71cSSimon Glass			};
138ce02a71cSSimon Glass			gpu {
139ce02a71cSSimon Glass				nvidia,pins = "gpu";
140ce02a71cSSimon Glass				nvidia,function = "pwm";
141ce02a71cSSimon Glass			};
142ce02a71cSSimon Glass			gpu7 {
143ce02a71cSSimon Glass				nvidia,pins = "gpu7";
144ce02a71cSSimon Glass				nvidia,function = "rtck";
145ce02a71cSSimon Glass			};
146ce02a71cSSimon Glass			gpv {
147ce02a71cSSimon Glass				nvidia,pins = "gpv", "slxa", "slxk";
148ce02a71cSSimon Glass				nvidia,function = "pcie";
149ce02a71cSSimon Glass			};
150ce02a71cSSimon Glass			hdint {
151ce02a71cSSimon Glass				nvidia,pins = "hdint";
152ce02a71cSSimon Glass				nvidia,function = "hdmi";
153ce02a71cSSimon Glass			};
154ce02a71cSSimon Glass			i2cp {
155ce02a71cSSimon Glass				nvidia,pins = "i2cp";
156ce02a71cSSimon Glass				nvidia,function = "i2cp";
157ce02a71cSSimon Glass			};
158ce02a71cSSimon Glass			irrx {
159ce02a71cSSimon Glass				nvidia,pins = "irrx", "irtx";
160ce02a71cSSimon Glass				nvidia,function = "uartb";
161ce02a71cSSimon Glass			};
162ce02a71cSSimon Glass			kbca {
163ce02a71cSSimon Glass				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
164ce02a71cSSimon Glass					"kbce", "kbcf";
165ce02a71cSSimon Glass				nvidia,function = "kbc";
166ce02a71cSSimon Glass			};
167ce02a71cSSimon Glass			lcsn {
168ce02a71cSSimon Glass				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
169ce02a71cSSimon Glass					"lsdi", "lvp0";
170ce02a71cSSimon Glass				nvidia,function = "rsvd4";
171ce02a71cSSimon Glass			};
172ce02a71cSSimon Glass			ld0 {
173ce02a71cSSimon Glass				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
174ce02a71cSSimon Glass					"ld5", "ld6", "ld7", "ld8", "ld9",
175ce02a71cSSimon Glass					"ld10", "ld11", "ld12", "ld13", "ld14",
176ce02a71cSSimon Glass					"ld15", "ld16", "ld17", "ldi", "lhp0",
177ce02a71cSSimon Glass					"lhp1", "lhp2", "lhs", "lpp", "lpw0",
178ce02a71cSSimon Glass					"lpw2", "lsc0", "lsc1", "lsck", "lsda",
179ce02a71cSSimon Glass					"lspi", "lvp1", "lvs";
180ce02a71cSSimon Glass				nvidia,function = "displaya";
181ce02a71cSSimon Glass			};
182ce02a71cSSimon Glass			owc {
183ce02a71cSSimon Glass				nvidia,pins = "owc", "spdi", "spdo", "uac";
184ce02a71cSSimon Glass				nvidia,function = "rsvd2";
185ce02a71cSSimon Glass			};
186ce02a71cSSimon Glass			pmc {
187ce02a71cSSimon Glass				nvidia,pins = "pmc";
188ce02a71cSSimon Glass				nvidia,function = "pwr_on";
189ce02a71cSSimon Glass			};
190ce02a71cSSimon Glass			rm {
191ce02a71cSSimon Glass				nvidia,pins = "rm";
192ce02a71cSSimon Glass				nvidia,function = "i2c1";
193ce02a71cSSimon Glass			};
194ce02a71cSSimon Glass			sdb {
195ce02a71cSSimon Glass				nvidia,pins = "sdb", "sdc", "sdd", "slxc";
196ce02a71cSSimon Glass				nvidia,function = "sdio3";
197ce02a71cSSimon Glass			};
198ce02a71cSSimon Glass			sdio1 {
199ce02a71cSSimon Glass				nvidia,pins = "sdio1";
200ce02a71cSSimon Glass				nvidia,function = "sdio1";
201ce02a71cSSimon Glass			};
202ce02a71cSSimon Glass			slxd {
203ce02a71cSSimon Glass				nvidia,pins = "slxd";
204ce02a71cSSimon Glass				nvidia,function = "spdif";
205ce02a71cSSimon Glass			};
206ce02a71cSSimon Glass			spid {
207ce02a71cSSimon Glass				nvidia,pins = "spid", "spie", "spif";
208ce02a71cSSimon Glass				nvidia,function = "spi1";
209ce02a71cSSimon Glass			};
210ce02a71cSSimon Glass			spig {
211ce02a71cSSimon Glass				nvidia,pins = "spig", "spih";
212ce02a71cSSimon Glass				nvidia,function = "spi2_alt";
213ce02a71cSSimon Glass			};
214ce02a71cSSimon Glass			uaa {
215ce02a71cSSimon Glass				nvidia,pins = "uaa", "uab", "uda";
216ce02a71cSSimon Glass				nvidia,function = "ulpi";
217ce02a71cSSimon Glass			};
218ce02a71cSSimon Glass			uad {
219ce02a71cSSimon Glass				nvidia,pins = "uad";
220ce02a71cSSimon Glass				nvidia,function = "irda";
221ce02a71cSSimon Glass			};
222ce02a71cSSimon Glass			uca {
223ce02a71cSSimon Glass				nvidia,pins = "uca", "ucb";
224ce02a71cSSimon Glass				nvidia,function = "uartc";
225ce02a71cSSimon Glass			};
226ce02a71cSSimon Glass			conf_ata {
227ce02a71cSSimon Glass				nvidia,pins = "ata", "atb", "atc", "atd",
228ce02a71cSSimon Glass					"cdev1", "cdev2", "dap1", "dap2",
229ce02a71cSSimon Glass					"dap4", "ddc", "dtf", "gma", "gmc",
230ce02a71cSSimon Glass					"gme", "gpu", "gpu7", "i2cp", "irrx",
231ce02a71cSSimon Glass					"irtx", "pta", "rm", "sdc", "sdd",
232ce02a71cSSimon Glass					"slxc", "slxd", "slxk", "spdi", "spdo",
233ce02a71cSSimon Glass					"uac", "uad", "uca", "ucb", "uda";
234ce02a71cSSimon Glass				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
235ce02a71cSSimon Glass				nvidia,tristate = <TEGRA_PIN_DISABLE>;
236ce02a71cSSimon Glass			};
237ce02a71cSSimon Glass			conf_ate {
238ce02a71cSSimon Glass				nvidia,pins = "ate", "csus", "dap3", "gmd",
239ce02a71cSSimon Glass					"gpv", "owc", "spia", "spib", "spic",
240ce02a71cSSimon Glass					"spid", "spie", "spig";
241ce02a71cSSimon Glass				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
242ce02a71cSSimon Glass				nvidia,tristate = <TEGRA_PIN_ENABLE>;
243ce02a71cSSimon Glass			};
244ce02a71cSSimon Glass			conf_ck32 {
245ce02a71cSSimon Glass				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
246ce02a71cSSimon Glass					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
247ce02a71cSSimon Glass				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
248ce02a71cSSimon Glass			};
249ce02a71cSSimon Glass			conf_crtp {
250ce02a71cSSimon Glass				nvidia,pins = "crtp", "gmb", "slxa", "spih";
251ce02a71cSSimon Glass				nvidia,pull = <TEGRA_PIN_PULL_UP>;
252ce02a71cSSimon Glass				nvidia,tristate = <TEGRA_PIN_ENABLE>;
253ce02a71cSSimon Glass			};
254ce02a71cSSimon Glass			conf_dta {
255ce02a71cSSimon Glass				nvidia,pins = "dta", "dtb", "dtc", "dtd";
256ce02a71cSSimon Glass				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
257ce02a71cSSimon Glass				nvidia,tristate = <TEGRA_PIN_DISABLE>;
258ce02a71cSSimon Glass			};
259ce02a71cSSimon Glass			conf_dte {
260ce02a71cSSimon Glass				nvidia,pins = "dte", "spif";
261ce02a71cSSimon Glass				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
262ce02a71cSSimon Glass				nvidia,tristate = <TEGRA_PIN_ENABLE>;
263ce02a71cSSimon Glass			};
264ce02a71cSSimon Glass			conf_hdint {
265ce02a71cSSimon Glass				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
266ce02a71cSSimon Glass					"lpw1", "lsck", "lsda", "lsdi", "lvp0";
267ce02a71cSSimon Glass				nvidia,tristate = <TEGRA_PIN_ENABLE>;
268ce02a71cSSimon Glass			};
269ce02a71cSSimon Glass			conf_kbca {
270ce02a71cSSimon Glass				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
271ce02a71cSSimon Glass					"kbce", "kbcf", "sdio1", "uaa", "uab";
272ce02a71cSSimon Glass				nvidia,pull = <TEGRA_PIN_PULL_UP>;
273ce02a71cSSimon Glass				nvidia,tristate = <TEGRA_PIN_DISABLE>;
274ce02a71cSSimon Glass			};
275ce02a71cSSimon Glass			conf_lc {
276ce02a71cSSimon Glass				nvidia,pins = "lc", "ls";
277ce02a71cSSimon Glass				nvidia,pull = <TEGRA_PIN_PULL_UP>;
278ce02a71cSSimon Glass			};
279ce02a71cSSimon Glass			conf_ld0 {
280ce02a71cSSimon Glass				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
281ce02a71cSSimon Glass					"ld5", "ld6", "ld7", "ld8", "ld9",
282ce02a71cSSimon Glass					"ld10", "ld11", "ld12", "ld13", "ld14",
283ce02a71cSSimon Glass					"ld15", "ld16", "ld17", "ldi", "lhp0",
284ce02a71cSSimon Glass					"lhp1", "lhp2", "lhs", "lm0", "lpp",
285ce02a71cSSimon Glass					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
286ce02a71cSSimon Glass					"lvp1", "lvs", "pmc", "sdb";
287ce02a71cSSimon Glass				nvidia,tristate = <TEGRA_PIN_DISABLE>;
288ce02a71cSSimon Glass			};
289ce02a71cSSimon Glass			conf_ld17_0 {
290ce02a71cSSimon Glass				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
291ce02a71cSSimon Glass					"ld23_22";
292ce02a71cSSimon Glass				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
293ce02a71cSSimon Glass			};
294ce02a71cSSimon Glass			drive_sdio1 {
295ce02a71cSSimon Glass				nvidia,pins = "drive_sdio1";
296ce02a71cSSimon Glass				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
297ce02a71cSSimon Glass				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
298ce02a71cSSimon Glass				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
299ce02a71cSSimon Glass				nvidia,pull-down-strength = <31>;
300ce02a71cSSimon Glass				nvidia,pull-up-strength = <31>;
301ce02a71cSSimon Glass				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
302ce02a71cSSimon Glass				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
303ce02a71cSSimon Glass			};
304ce02a71cSSimon Glass		};
305ce02a71cSSimon Glass
306ce02a71cSSimon Glass		state_i2cmux_ddc: pinmux_i2cmux_ddc {
307ce02a71cSSimon Glass			ddc {
308ce02a71cSSimon Glass				nvidia,pins = "ddc";
309ce02a71cSSimon Glass				nvidia,function = "i2c2";
310ce02a71cSSimon Glass			};
311ce02a71cSSimon Glass			pta {
312ce02a71cSSimon Glass				nvidia,pins = "pta";
313ce02a71cSSimon Glass				nvidia,function = "rsvd4";
314ce02a71cSSimon Glass			};
315ce02a71cSSimon Glass		};
316ce02a71cSSimon Glass
317ce02a71cSSimon Glass		state_i2cmux_pta: pinmux_i2cmux_pta {
318ce02a71cSSimon Glass			ddc {
319ce02a71cSSimon Glass				nvidia,pins = "ddc";
320ce02a71cSSimon Glass				nvidia,function = "rsvd4";
321ce02a71cSSimon Glass			};
322ce02a71cSSimon Glass			pta {
323ce02a71cSSimon Glass				nvidia,pins = "pta";
324ce02a71cSSimon Glass				nvidia,function = "i2c2";
325ce02a71cSSimon Glass			};
326ce02a71cSSimon Glass		};
327ce02a71cSSimon Glass
328ce02a71cSSimon Glass		state_i2cmux_idle: pinmux_i2cmux_idle {
329ce02a71cSSimon Glass			ddc {
330ce02a71cSSimon Glass				nvidia,pins = "ddc";
331ce02a71cSSimon Glass				nvidia,function = "rsvd4";
332ce02a71cSSimon Glass			};
333ce02a71cSSimon Glass			pta {
334ce02a71cSSimon Glass				nvidia,pins = "pta";
335ce02a71cSSimon Glass				nvidia,function = "rsvd4";
336ce02a71cSSimon Glass			};
337ce02a71cSSimon Glass		};
338ce02a71cSSimon Glass	};
339ce02a71cSSimon Glass
340ce02a71cSSimon Glass	i2s@70002800 {
341ce02a71cSSimon Glass		status = "okay";
3425ab502cbSMasahiro Yamada	};
3435ab502cbSMasahiro Yamada
3445ab502cbSMasahiro Yamada	serial@70006300 {
345ce02a71cSSimon Glass		status = "okay";
346ce02a71cSSimon Glass		clock-frequency = < 216000000 >;	};
347ce02a71cSSimon Glass
348ce02a71cSSimon Glass	pwm: pwm@7000a000 {
349ce02a71cSSimon Glass		status = "okay";
350ce02a71cSSimon Glass	};
351ce02a71cSSimon Glass
352ce02a71cSSimon Glass	i2c@7000c000 {
353ce02a71cSSimon Glass		status = "okay";
354ce02a71cSSimon Glass		clock-frequency = <400000>;
355ce02a71cSSimon Glass
356ce02a71cSSimon Glass		wm8903: wm8903@1a {
357ce02a71cSSimon Glass			compatible = "wlf,wm8903";
358ce02a71cSSimon Glass			reg = <0x1a>;
359ce02a71cSSimon Glass			interrupt-parent = <&gpio>;
360ce02a71cSSimon Glass			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
361ce02a71cSSimon Glass
362ce02a71cSSimon Glass			gpio-controller;
363ce02a71cSSimon Glass			#gpio-cells = <2>;
364ce02a71cSSimon Glass
365ce02a71cSSimon Glass			micdet-cfg = <0>;
366ce02a71cSSimon Glass			micdet-delay = <100>;
367ce02a71cSSimon Glass			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
368ce02a71cSSimon Glass		};
369ce02a71cSSimon Glass
370ce02a71cSSimon Glass		/* ALS and proximity sensor */
371ce02a71cSSimon Glass		isl29018@44 {
372ce02a71cSSimon Glass			compatible = "isil,isl29018";
373ce02a71cSSimon Glass			reg = <0x44>;
374ce02a71cSSimon Glass			interrupt-parent = <&gpio>;
375ce02a71cSSimon Glass			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
376ce02a71cSSimon Glass		};
377ce02a71cSSimon Glass	};
378ce02a71cSSimon Glass
379ce02a71cSSimon Glass	i2c@7000c400 {
380ce02a71cSSimon Glass		status = "okay";
381ce02a71cSSimon Glass		clock-frequency = <100000>;
382ce02a71cSSimon Glass	};
383ce02a71cSSimon Glass
384ce02a71cSSimon Glass	i2cmux {
385ce02a71cSSimon Glass		compatible = "i2c-mux-pinctrl";
386ce02a71cSSimon Glass		#address-cells = <1>;
387ce02a71cSSimon Glass		#size-cells = <0>;
388ce02a71cSSimon Glass
389ce02a71cSSimon Glass		i2c-parent = <&{/i2c@7000c400}>;
390ce02a71cSSimon Glass
391ce02a71cSSimon Glass		pinctrl-names = "ddc", "pta", "idle";
392ce02a71cSSimon Glass		pinctrl-0 = <&state_i2cmux_ddc>;
393ce02a71cSSimon Glass		pinctrl-1 = <&state_i2cmux_pta>;
394ce02a71cSSimon Glass		pinctrl-2 = <&state_i2cmux_idle>;
395ce02a71cSSimon Glass
396ce02a71cSSimon Glass		hdmi_ddc: i2c@0 {
397ce02a71cSSimon Glass			reg = <0>;
398ce02a71cSSimon Glass			#address-cells = <1>;
399ce02a71cSSimon Glass			#size-cells = <0>;
400ce02a71cSSimon Glass		};
401ce02a71cSSimon Glass
402ce02a71cSSimon Glass		lvds_ddc: i2c@1 {
403ce02a71cSSimon Glass			reg = <1>;
404ce02a71cSSimon Glass			#address-cells = <1>;
405ce02a71cSSimon Glass			#size-cells = <0>;
406ce02a71cSSimon Glass		};
407ce02a71cSSimon Glass	};
408ce02a71cSSimon Glass
409ce02a71cSSimon Glass	i2c@7000c500 {
410ce02a71cSSimon Glass		status = "okay";
411ce02a71cSSimon Glass		clock-frequency = <400000>;
412ce02a71cSSimon Glass	};
413ce02a71cSSimon Glass
414ce02a71cSSimon Glass	i2c@7000d000 {
415ce02a71cSSimon Glass		status = "okay";
416ce02a71cSSimon Glass		clock-frequency = <400000>;
417ce02a71cSSimon Glass
418ce02a71cSSimon Glass		pmic: tps6586x@34 {
419ce02a71cSSimon Glass			compatible = "ti,tps6586x";
420ce02a71cSSimon Glass			reg = <0x34>;
421ce02a71cSSimon Glass			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
422ce02a71cSSimon Glass
423ce02a71cSSimon Glass			ti,system-power-controller;
424ce02a71cSSimon Glass
425ce02a71cSSimon Glass			#gpio-cells = <2>;
426ce02a71cSSimon Glass			gpio-controller;
427ce02a71cSSimon Glass
428ce02a71cSSimon Glass			sys-supply = <&vdd_5v0_reg>;
429ce02a71cSSimon Glass			vin-sm0-supply = <&sys_reg>;
430ce02a71cSSimon Glass			vin-sm1-supply = <&sys_reg>;
431ce02a71cSSimon Glass			vin-sm2-supply = <&sys_reg>;
432ce02a71cSSimon Glass			vinldo01-supply = <&sm2_reg>;
433ce02a71cSSimon Glass			vinldo23-supply = <&sm2_reg>;
434ce02a71cSSimon Glass			vinldo4-supply = <&sm2_reg>;
435ce02a71cSSimon Glass			vinldo678-supply = <&sm2_reg>;
436ce02a71cSSimon Glass			vinldo9-supply = <&sm2_reg>;
437ce02a71cSSimon Glass
438ce02a71cSSimon Glass			regulators {
439ce02a71cSSimon Glass				sys_reg: sys {
440ce02a71cSSimon Glass					regulator-name = "vdd_sys";
441ce02a71cSSimon Glass					regulator-always-on;
442ce02a71cSSimon Glass				};
443ce02a71cSSimon Glass
444ce02a71cSSimon Glass				sm0 {
445ce02a71cSSimon Glass					regulator-name = "vdd_sm0,vdd_core";
446ce02a71cSSimon Glass					regulator-min-microvolt = <1200000>;
447ce02a71cSSimon Glass					regulator-max-microvolt = <1200000>;
448ce02a71cSSimon Glass					regulator-always-on;
449ce02a71cSSimon Glass				};
450ce02a71cSSimon Glass
451ce02a71cSSimon Glass				sm1 {
452ce02a71cSSimon Glass					regulator-name = "vdd_sm1,vdd_cpu";
453ce02a71cSSimon Glass					regulator-min-microvolt = <1000000>;
454ce02a71cSSimon Glass					regulator-max-microvolt = <1000000>;
455ce02a71cSSimon Glass					regulator-always-on;
456ce02a71cSSimon Glass				};
457ce02a71cSSimon Glass
458ce02a71cSSimon Glass				sm2_reg: sm2 {
459ce02a71cSSimon Glass					regulator-name = "vdd_sm2,vin_ldo*";
460ce02a71cSSimon Glass					regulator-min-microvolt = <3700000>;
461ce02a71cSSimon Glass					regulator-max-microvolt = <3700000>;
462ce02a71cSSimon Glass					regulator-always-on;
463ce02a71cSSimon Glass				};
464ce02a71cSSimon Glass
465ce02a71cSSimon Glass				/* LDO0 is not connected to anything */
466ce02a71cSSimon Glass
467ce02a71cSSimon Glass				ldo1 {
468ce02a71cSSimon Glass					regulator-name = "vdd_ldo1,avdd_pll*";
469ce02a71cSSimon Glass					regulator-min-microvolt = <1100000>;
470ce02a71cSSimon Glass					regulator-max-microvolt = <1100000>;
471ce02a71cSSimon Glass					regulator-always-on;
472ce02a71cSSimon Glass				};
473ce02a71cSSimon Glass
474ce02a71cSSimon Glass				ldo2 {
475ce02a71cSSimon Glass					regulator-name = "vdd_ldo2,vdd_rtc";
476ce02a71cSSimon Glass					regulator-min-microvolt = <1200000>;
477ce02a71cSSimon Glass					regulator-max-microvolt = <1200000>;
478ce02a71cSSimon Glass				};
479ce02a71cSSimon Glass
480ce02a71cSSimon Glass				ldo3 {
481ce02a71cSSimon Glass					regulator-name = "vdd_ldo3,avdd_usb*";
482ce02a71cSSimon Glass					regulator-min-microvolt = <3300000>;
483ce02a71cSSimon Glass					regulator-max-microvolt = <3300000>;
484ce02a71cSSimon Glass					regulator-always-on;
485ce02a71cSSimon Glass				};
486ce02a71cSSimon Glass
487ce02a71cSSimon Glass				ldo4 {
488ce02a71cSSimon Glass					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
489ce02a71cSSimon Glass					regulator-min-microvolt = <1800000>;
490ce02a71cSSimon Glass					regulator-max-microvolt = <1800000>;
491ce02a71cSSimon Glass					regulator-always-on;
492ce02a71cSSimon Glass				};
493ce02a71cSSimon Glass
494ce02a71cSSimon Glass				ldo5 {
495ce02a71cSSimon Glass					regulator-name = "vdd_ldo5,vcore_mmc";
496ce02a71cSSimon Glass					regulator-min-microvolt = <2850000>;
497ce02a71cSSimon Glass					regulator-max-microvolt = <2850000>;
498ce02a71cSSimon Glass					regulator-always-on;
499ce02a71cSSimon Glass				};
500ce02a71cSSimon Glass
501ce02a71cSSimon Glass				ldo6 {
502ce02a71cSSimon Glass					regulator-name = "vdd_ldo6,avdd_vdac";
503ce02a71cSSimon Glass					regulator-min-microvolt = <1800000>;
504ce02a71cSSimon Glass					regulator-max-microvolt = <1800000>;
505ce02a71cSSimon Glass				};
506ce02a71cSSimon Glass
507ce02a71cSSimon Glass				hdmi_vdd_reg: ldo7 {
508ce02a71cSSimon Glass					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
509ce02a71cSSimon Glass					regulator-min-microvolt = <3300000>;
510ce02a71cSSimon Glass					regulator-max-microvolt = <3300000>;
511ce02a71cSSimon Glass				};
512ce02a71cSSimon Glass
513ce02a71cSSimon Glass				hdmi_pll_reg: ldo8 {
514ce02a71cSSimon Glass					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
515ce02a71cSSimon Glass					regulator-min-microvolt = <1800000>;
516ce02a71cSSimon Glass					regulator-max-microvolt = <1800000>;
517ce02a71cSSimon Glass				};
518ce02a71cSSimon Glass
519ce02a71cSSimon Glass				ldo9 {
520ce02a71cSSimon Glass					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
521ce02a71cSSimon Glass					regulator-min-microvolt = <2850000>;
522ce02a71cSSimon Glass					regulator-max-microvolt = <2850000>;
523ce02a71cSSimon Glass					regulator-always-on;
524ce02a71cSSimon Glass				};
525ce02a71cSSimon Glass
526ce02a71cSSimon Glass				ldo_rtc {
527ce02a71cSSimon Glass					regulator-name = "vdd_rtc_out,vdd_cell";
528ce02a71cSSimon Glass					regulator-min-microvolt = <3300000>;
529ce02a71cSSimon Glass					regulator-max-microvolt = <3300000>;
530ce02a71cSSimon Glass					regulator-always-on;
531ce02a71cSSimon Glass				};
532ce02a71cSSimon Glass			};
533ce02a71cSSimon Glass		};
534ce02a71cSSimon Glass
535ce02a71cSSimon Glass		temperature-sensor@4c {
536ce02a71cSSimon Glass			compatible = "onnn,nct1008";
537ce02a71cSSimon Glass			reg = <0x4c>;
538ce02a71cSSimon Glass		};
539ce02a71cSSimon Glass	};
540ce02a71cSSimon Glass
541ce02a71cSSimon Glass	pmc@7000e400 {
542ce02a71cSSimon Glass		nvidia,invert-interrupt;
543ce02a71cSSimon Glass		nvidia,suspend-mode = <1>;
544ce02a71cSSimon Glass		nvidia,cpu-pwr-good-time = <2000>;
545ce02a71cSSimon Glass		nvidia,cpu-pwr-off-time = <100>;
546ce02a71cSSimon Glass		nvidia,core-pwr-good-time = <3845 3845>;
547ce02a71cSSimon Glass		nvidia,core-pwr-off-time = <458>;
548ce02a71cSSimon Glass		nvidia,sys-clock-req-active-high;
549ce02a71cSSimon Glass	};
550ce02a71cSSimon Glass
551ce02a71cSSimon Glass	usb@c5000000 {
552ce02a71cSSimon Glass		status = "okay";
553ce02a71cSSimon Glass	};
554ce02a71cSSimon Glass
555ce02a71cSSimon Glass	usb-phy@c5000000 {
556ce02a71cSSimon Glass		status = "okay";
557ce02a71cSSimon Glass	};
558ce02a71cSSimon Glass
559ce02a71cSSimon Glass	usb@c5004000 {
560ce02a71cSSimon Glass		status = "okay";
561ce02a71cSSimon Glass		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
562ce02a71cSSimon Glass			GPIO_ACTIVE_LOW>;
563ce02a71cSSimon Glass	};
564ce02a71cSSimon Glass
565ce02a71cSSimon Glass	usb-phy@c5004000 {
566ce02a71cSSimon Glass		status = "okay";
567ce02a71cSSimon Glass		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
568ce02a71cSSimon Glass			GPIO_ACTIVE_LOW>;
5695ab502cbSMasahiro Yamada	};
5705ab502cbSMasahiro Yamada
571ee7d755aSSimon Glass	usb@c5008000 {
572ee7d755aSSimon Glass		status = "okay";
5735ab502cbSMasahiro Yamada	};
5745ab502cbSMasahiro Yamada
575ce02a71cSSimon Glass	usb-phy@c5008000 {
576ce02a71cSSimon Glass		status = "okay";
577ce02a71cSSimon Glass	};
578ce02a71cSSimon Glass
579ce02a71cSSimon Glass	sdhci@c8000000 {
580ce02a71cSSimon Glass		status = "okay";
581ce02a71cSSimon Glass		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
582ce02a71cSSimon Glass		bus-width = <4>;
583ce02a71cSSimon Glass		keep-power-in-suspend;
584ce02a71cSSimon Glass	};
585ce02a71cSSimon Glass
5865ab502cbSMasahiro Yamada	sdhci@c8000400 {
5875ab502cbSMasahiro Yamada		status = "okay";
5882b2b50bcSSimon Glass		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
5892b2b50bcSSimon Glass		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
5902b2b50bcSSimon Glass		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
5915ab502cbSMasahiro Yamada		bus-width = <4>;
5925ab502cbSMasahiro Yamada	};
5935ab502cbSMasahiro Yamada
5945ab502cbSMasahiro Yamada	sdhci@c8000600 {
5955ab502cbSMasahiro Yamada		status = "okay";
5965ab502cbSMasahiro Yamada		bus-width = <8>;
597ce02a71cSSimon Glass		non-removable;
598ce02a71cSSimon Glass	};
599ce02a71cSSimon Glass
600ce02a71cSSimon Glass	backlight: backlight {
601ce02a71cSSimon Glass		compatible = "pwm-backlight";
602ce02a71cSSimon Glass
603ce02a71cSSimon Glass		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
604ce02a71cSSimon Glass		power-supply = <&vdd_bl_reg>;
605ce02a71cSSimon Glass		pwms = <&pwm 2 5000000>;
606ce02a71cSSimon Glass
607ce02a71cSSimon Glass		brightness-levels = <0 4 8 16 32 64 128 255>;
608ce02a71cSSimon Glass		default-brightness-level = <6>;
6095ab502cbSMasahiro Yamada	};
6105ab502cbSMasahiro Yamada
611ee7d755aSSimon Glass	clocks {
612ee7d755aSSimon Glass		compatible = "simple-bus";
613ee7d755aSSimon Glass		#address-cells = <1>;
614ee7d755aSSimon Glass		#size-cells = <0>;
615ee7d755aSSimon Glass
616ee7d755aSSimon Glass		clk32k_in: clock@0 {
617ee7d755aSSimon Glass			compatible = "fixed-clock";
618ee7d755aSSimon Glass			reg=<0>;
619ee7d755aSSimon Glass			#clock-cells = <0>;
620ee7d755aSSimon Glass			clock-frequency = <32768>;
621ee7d755aSSimon Glass		};
622ee7d755aSSimon Glass	};
623ee7d755aSSimon Glass
624ce02a71cSSimon Glass	gpio-keys {
625ce02a71cSSimon Glass		compatible = "gpio-keys";
626ce02a71cSSimon Glass
627ce02a71cSSimon Glass		power {
628ce02a71cSSimon Glass			label = "Power";
629ce02a71cSSimon Glass			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
630ce02a71cSSimon Glass			linux,code = <KEY_POWER>;
631ce02a71cSSimon Glass			gpio-key,wakeup;
632ce02a71cSSimon Glass		};
633ce02a71cSSimon Glass	};
634ce02a71cSSimon Glass
635ec550770SSimon Glass	panel: panel {
636ec550770SSimon Glass		compatible = "chunghwa,claa101wa01a", "simple-panel";
637ec550770SSimon Glass
638ec550770SSimon Glass		power-supply = <&vdd_pnl_reg>;
639ec550770SSimon Glass		enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
640ec550770SSimon Glass
641ec550770SSimon Glass		backlight = <&backlight>;
642ec550770SSimon Glass		ddc-i2c-bus = <&lvds_ddc>;
643ec550770SSimon Glass	};
644ec550770SSimon Glass
645ce02a71cSSimon Glass	regulators {
646ce02a71cSSimon Glass		compatible = "simple-bus";
647ce02a71cSSimon Glass		#address-cells = <1>;
648ce02a71cSSimon Glass		#size-cells = <0>;
649ce02a71cSSimon Glass
650ce02a71cSSimon Glass		vdd_5v0_reg: regulator@0 {
651ce02a71cSSimon Glass			compatible = "regulator-fixed";
652ce02a71cSSimon Glass			reg = <0>;
653ce02a71cSSimon Glass			regulator-name = "vdd_5v0";
654ce02a71cSSimon Glass			regulator-min-microvolt = <5000000>;
655ce02a71cSSimon Glass			regulator-max-microvolt = <5000000>;
656ce02a71cSSimon Glass			regulator-always-on;
657ce02a71cSSimon Glass		};
658ce02a71cSSimon Glass
659ce02a71cSSimon Glass		regulator@1 {
660ce02a71cSSimon Glass			compatible = "regulator-fixed";
661ce02a71cSSimon Glass			reg = <1>;
662ce02a71cSSimon Glass			regulator-name = "vdd_1v5";
663ce02a71cSSimon Glass			regulator-min-microvolt = <1500000>;
664ce02a71cSSimon Glass			regulator-max-microvolt = <1500000>;
665ce02a71cSSimon Glass			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
666ce02a71cSSimon Glass		};
667ce02a71cSSimon Glass
668ce02a71cSSimon Glass		regulator@2 {
669ce02a71cSSimon Glass			compatible = "regulator-fixed";
670ce02a71cSSimon Glass			reg = <2>;
671ce02a71cSSimon Glass			regulator-name = "vdd_1v2";
672ce02a71cSSimon Glass			regulator-min-microvolt = <1200000>;
673ce02a71cSSimon Glass			regulator-max-microvolt = <1200000>;
674ce02a71cSSimon Glass			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
675ce02a71cSSimon Glass			enable-active-high;
676ce02a71cSSimon Glass		};
677ce02a71cSSimon Glass
678ce02a71cSSimon Glass		vdd_pnl_reg: regulator@3 {
679ce02a71cSSimon Glass			compatible = "regulator-fixed";
680ce02a71cSSimon Glass			reg = <3>;
681ce02a71cSSimon Glass			regulator-name = "vdd_pnl";
682ce02a71cSSimon Glass			regulator-min-microvolt = <2800000>;
683ce02a71cSSimon Glass			regulator-max-microvolt = <2800000>;
684ce02a71cSSimon Glass			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
685ce02a71cSSimon Glass			enable-active-high;
686ce02a71cSSimon Glass		};
687ce02a71cSSimon Glass
688ce02a71cSSimon Glass		vdd_bl_reg: regulator@4 {
689ce02a71cSSimon Glass			compatible = "regulator-fixed";
690ce02a71cSSimon Glass			reg = <4>;
691ce02a71cSSimon Glass			regulator-name = "vdd_bl";
692ce02a71cSSimon Glass			regulator-min-microvolt = <2800000>;
693ce02a71cSSimon Glass			regulator-max-microvolt = <2800000>;
694ce02a71cSSimon Glass			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
695ce02a71cSSimon Glass			enable-active-high;
696ce02a71cSSimon Glass		};
69791c08afeSSimon Glass	};
69891c08afeSSimon Glass
699ce02a71cSSimon Glass	sound {
700ce02a71cSSimon Glass		compatible = "nvidia,tegra-audio-wm8903-ventana",
701ce02a71cSSimon Glass			     "nvidia,tegra-audio-wm8903";
702ce02a71cSSimon Glass		nvidia,model = "NVIDIA Tegra Ventana";
703ce02a71cSSimon Glass
704ce02a71cSSimon Glass		nvidia,audio-routing =
705ce02a71cSSimon Glass			"Headphone Jack", "HPOUTR",
706ce02a71cSSimon Glass			"Headphone Jack", "HPOUTL",
707ce02a71cSSimon Glass			"Int Spk", "ROP",
708ce02a71cSSimon Glass			"Int Spk", "RON",
709ce02a71cSSimon Glass			"Int Spk", "LOP",
710ce02a71cSSimon Glass			"Int Spk", "LON",
711ce02a71cSSimon Glass			"Mic Jack", "MICBIAS",
712ce02a71cSSimon Glass			"IN1L", "Mic Jack";
713ce02a71cSSimon Glass
714ce02a71cSSimon Glass		nvidia,i2s-controller = <&tegra_i2s1>;
715ce02a71cSSimon Glass		nvidia,audio-codec = <&wm8903>;
716ce02a71cSSimon Glass
717ce02a71cSSimon Glass		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
718ce02a71cSSimon Glass		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
719ce02a71cSSimon Glass		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
720ce02a71cSSimon Glass			GPIO_ACTIVE_HIGH>;
721ce02a71cSSimon Glass		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
722ce02a71cSSimon Glass			GPIO_ACTIVE_HIGH>;
723ce02a71cSSimon Glass
724ce02a71cSSimon Glass		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
725ce02a71cSSimon Glass			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
726ce02a71cSSimon Glass			 <&tegra_car TEGRA20_CLK_CDEV1>;
727ce02a71cSSimon Glass		clock-names = "pll_a", "pll_a_out0", "mclk";
728ce02a71cSSimon Glass	};
7295ab502cbSMasahiro Yamada};
730