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Searched refs:freq (Results 1 – 25 of 235) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/mach-imx/
H A Dsyscounter.c37 unsigned long freq; in tick_to_time() local
39 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); in tick_to_time()
42 do_div(tick, freq); in tick_to_time()
49 unsigned long freq; in us_to_tick() local
51 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); in us_to_tick()
53 usec = usec * freq + 999999; in us_to_tick()
62 unsigned long val, freq; in timer_init() local
64 freq = CONFIG_SC_TIMER_CLK; in timer_init()
65 asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); in timer_init()
67 writel(freq, &sctr->cntfid0); in timer_init()
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/rk3399_rockchip-uboot/arch/arm/cpu/armv7/ls102xa/
H A Dtimer.c34 unsigned long freq; in tick_to_time() local
36 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); in tick_to_time()
39 do_div(tick, freq); in tick_to_time()
46 unsigned long freq; in us_to_tick() local
48 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); in us_to_tick()
50 usec = usec * freq + 999999; in us_to_tick()
59 unsigned long ctrl, freq; in timer_init() local
65 freq = COUNTER_FREQUENCY; in timer_init()
66 asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); in timer_init()
123 unsigned long freq; in get_tbclk() local
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/rk3399_rockchip-uboot/arch/arm/cpu/armv8/s32v234/
H A Dgeneric.c98 u32 freq = 0; in get_mcu_main_clk() local
110 freq = FIRC_CLK_FREQ; in get_mcu_main_clk()
113 freq = XOSC_CLK_FREQ; in get_mcu_main_clk()
117 freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0); in get_mcu_main_clk()
126 return freq / coreclk_div; in get_mcu_main_clk()
133 u32 freq = 0; in get_sys_clk() local
157 freq = FIRC_CLK_FREQ; in get_sys_clk()
160 freq = XOSC_CLK_FREQ; in get_sys_clk()
164 freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1); in get_sys_clk()
173 return freq / sysclk_div; in get_sys_clk()
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/rk3399_rockchip-uboot/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c44 u32 freq = 0; in get_mcu_main_clk() local
57 freq = FASE_CLK_FREQ; in get_mcu_main_clk()
60 freq = SLOW_CLK_FREQ; in get_mcu_main_clk()
66 freq = PLL2_MAIN_FREQ; in get_mcu_main_clk()
68 freq = PLL2_PFD1_FREQ; in get_mcu_main_clk()
70 freq = PLL2_PFD2_FREQ; in get_mcu_main_clk()
72 freq = PLL2_PFD3_FREQ; in get_mcu_main_clk()
74 freq = PLL2_PFD4_FREQ; in get_mcu_main_clk()
77 freq = PLL2_MAIN_FREQ; in get_mcu_main_clk()
83 freq = PLL1_MAIN_FREQ; in get_mcu_main_clk()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-at91/armv7/
H A Dclock.c40 static u32 at91_pll_rate(u32 freq, u32 reg) in at91_pll_rate() argument
47 freq /= div; in at91_pll_rate()
48 freq *= mul + 1; in at91_pll_rate()
50 freq = 0; in at91_pll_rate()
53 return freq; in at91_pll_rate()
58 unsigned freq, mckr; in at91_clock_init() local
92 freq = gd->arch.mck_rate_hz; in at91_clock_init()
95 freq >>= mckr & AT91_PMC_MCKR_PRES_MASK; in at91_clock_init()
99 gd->arch.mck_rate_hz = freq / 2; in at91_clock_init()
102 gd->arch.mck_rate_hz = freq / 3; in at91_clock_init()
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/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_a38x.c199 enum hws_ddr_freq freq);
232 int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq, in ddr3_tip_a38x_get_freq_config() argument
236 if (a38x_bw_per_freq[freq] == 0xff) in ddr3_tip_a38x_get_freq_config()
242 freq_config_info->bw_per_freq = a38x_bw_per_freq[freq]; in ddr3_tip_a38x_get_freq_config()
243 freq_config_info->rate_per_freq = a38x_rate_per_freq[freq]; in ddr3_tip_a38x_get_freq_config()
451 enum hws_ddr_freq freq; in ddr3_a38x_update_topology_map() local
453 ddr3_tip_a38x_get_init_freq(dev_num, &freq); in ddr3_a38x_update_topology_map()
454 tm->interface_params[if_id].memory_freq = freq; in ddr3_a38x_update_topology_map()
478 int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq) in ddr3_tip_a38x_get_init_freq() argument
489 *freq = DDR_FREQ_333; in ddr3_tip_a38x_get_init_freq()
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/rk3399_rockchip-uboot/arch/arm/mach-imx/mx5/
H A Dclock.c255 u32 reg, freq; in get_mcu_main_clk() local
258 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
259 return freq / (reg + 1); in get_mcu_main_clk()
291 uint32_t freq, reg, div; in get_ipg_clk() local
293 freq = get_ahb_clk(); in get_ipg_clk()
298 return freq / div; in get_ipg_clk()
306 u32 freq, pred1, pred2, podf; in get_ipg_per_clk() local
312 freq = get_lp_apm(); in get_ipg_per_clk()
314 freq = get_periph_clk(); in get_ipg_per_clk()
319 return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); in get_ipg_per_clk()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-keystone/
H A Dclock.c346 unsigned long freq = 0; in ks_clk_get_rate() local
350 freq = pll_freq_get(CORE_PLL); in ks_clk_get_rate()
353 freq = pll_freq_get(PASS_PLL); in ks_clk_get_rate()
357 freq = pll_freq_get(TETRIS_PLL); in ks_clk_get_rate()
360 freq = pll_freq_get(DDR3A_PLL); in ks_clk_get_rate()
364 freq = pll_freq_get(DDR3B_PLL); in ks_clk_get_rate()
368 freq = pll_freq_get(UART_PLL); in ks_clk_get_rate()
372 freq = pll_freq_get(CORE_PLL) / pll0div_read(1); in ks_clk_get_rate()
378 freq = pll_freq_get(CORE_PLL) / pll0div_read(3); in ks_clk_get_rate()
381 freq = pll_freq_get(CORE_PLL) / pll0div_read(4); in ks_clk_get_rate()
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H A Dcmd_mon.c19 u32 addr, dpsc_base = 0x1E80000, freq, load_addr, size; in do_mon_install() local
27 freq = CONFIG_SYS_HZ_CLOCK; in do_mon_install()
46 rcode = mon_install(load_addr, dpsc_base, freq, ecrypt_bm_addr); in do_mon_install()
48 load_addr, freq, rcode); in do_mon_install()
/rk3399_rockchip-uboot/arch/arm/mach-at91/arm926ejs/
H A Dclock.c99 static u32 at91_pll_rate(u32 freq, u32 reg) in at91_pll_rate() argument
106 freq /= div; in at91_pll_rate()
107 freq *= mul + 1; in at91_pll_rate()
109 freq = 0; in at91_pll_rate()
111 return freq; in at91_pll_rate()
116 unsigned freq, mckr; in at91_clock_init() local
163 freq = gd->arch.mck_rate_hz; in at91_clock_init()
167 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4)); in at91_clock_init()
169 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ in at91_clock_init()
175 freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; in at91_clock_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-at91/arm920t/
H A Dclock.c91 static u32 at91_pll_rate(u32 freq, u32 reg) in at91_pll_rate() argument
98 freq /= div; in at91_pll_rate()
99 freq *= mul + 1; in at91_pll_rate()
101 freq = 0; in at91_pll_rate()
103 return freq; in at91_pll_rate()
108 unsigned freq, mckr; in at91_clock_init() local
150 freq = gd->arch.mck_rate_hz; in at91_clock_init()
152 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ in at91_clock_init()
154 gd->arch.mck_rate_hz = freq / in at91_clock_init()
156 gd->arch.cpu_clk_rate_hz = freq; in at91_clock_init()
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/dram/
H A Dumc-pxs2.c142 static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width, in ddrphy_init() argument
160 tmp = ddrphy_pgcr2[freq]; in ddrphy_init()
165 writel(ddrphy_ptr0[freq], phy_base + MPHY_PTR0); in ddrphy_init()
166 writel(ddrphy_ptr1[freq], phy_base + MPHY_PTR1); in ddrphy_init()
168 writel(ddrphy_ptr3[freq], phy_base + MPHY_PTR3); in ddrphy_init()
169 writel(ddrphy_ptr4[freq], phy_base + MPHY_PTR4); in ddrphy_init()
182 writel(ddrphy_dtpr0[freq], phy_base + MPHY_DTPR0); in ddrphy_init()
183 writel(ddrphy_dtpr1[freq], phy_base + MPHY_DTPR1); in ddrphy_init()
184 writel(ddrphy_dtpr2[freq], phy_base + MPHY_DTPR2); in ddrphy_init()
185 writel(ddrphy_dtpr3[freq], phy_base + MPHY_DTPR3); in ddrphy_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx7/
H A Dclock.c185 u32 freq, div, frac; in mxc_get_pll_sys_derive() local
190 freq = decode_pll(PLL_SYS, MXC_HCLK); in mxc_get_pll_sys_derive()
197 return freq; in mxc_get_pll_sys_derive()
202 return freq / 2; in mxc_get_pll_sys_derive()
207 return freq / 4; in mxc_get_pll_sys_derive()
293 return ((freq / frac) * 18) / div; in mxc_get_pll_sys_derive()
298 u32 freq, reg; in mxc_get_pll_enet_derive() local
300 freq = decode_pll(PLL_ENET, MXC_HCLK); in mxc_get_pll_enet_derive()
306 return freq / 2; in mxc_get_pll_enet_derive()
310 return freq / 4; in mxc_get_pll_enet_derive()
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/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c84 u32 freq, reg; in ddr3_hw_training() local
162 freq = dram_info.target_frequency; in ddr3_hw_training()
192 freq = DDR_100; in ddr3_hw_training()
195 freq = DDR_300; in ddr3_hw_training()
197 if (MV_OK != ddr3_dfs_high_2_low(freq, &dram_info)) { in ddr3_hw_training()
206 ddr3_write_leveling_hw_reg_dimm(freq, in ddr3_hw_training()
212 ddr3_print_freq(freq); in ddr3_hw_training()
232 freq, tmp_ratio, in ddr3_hw_training()
239 ddr3_write_leveling_hw(freq, in ddr3_hw_training()
247 freq, &dram_info)) { in ddr3_hw_training()
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/rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/
H A Dclock.c283 u64 freq; in mxc_get_pll_pfd() local
294 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK); in mxc_get_pll_pfd()
298 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK); in mxc_get_pll_pfd()
305 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> in mxc_get_pll_pfd()
311 u32 reg, freq; in get_mcu_main_clk() local
316 freq = decode_pll(PLL_SYS, MXC_HCLK); in get_mcu_main_clk()
318 return freq / (reg + 1); in get_mcu_main_clk()
323 u32 reg, div = 0, freq = 0; in get_periph_clk() local
335 freq = decode_pll(PLL_USBOTG, MXC_HCLK); in get_periph_clk()
339 freq = MXC_HCLK; in get_periph_clk()
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/rk3399_rockchip-uboot/drivers/sound/
H A Dsound.c11 void sound_create_square_wave(unsigned short *data, int size, uint32_t freq) in sound_create_square_wave() argument
15 const int period = freq ? sample / freq : 0; in sound_create_square_wave()
18 assert(freq); in sound_create_square_wave()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Ddmc-rk3368.c366 static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq) in ddrphy_config_delays() argument
385 if (freq <= 400000000) in ddrphy_config_delays()
390 if (freq < 681000000) in ddrphy_config_delays()
434 static inline u32 ps_to_tCK(const u32 ps, const ulong freq) in ps_to_tCK() argument
437 return DIV_ROUND_UP(ps * freq, 1000000 * MHz); in ps_to_tCK()
440 static inline u32 ns_to_tCK(const u32 ns, const ulong freq) in ns_to_tCK() argument
442 return ps_to_tCK(ns * 1000, freq); in ns_to_tCK()
445 static inline u32 tCK_to_ps(const ulong tCK, const ulong freq) in tCK_to_ps() argument
448 return DIV_ROUND_UP(tCK * 1000000 * MHz, freq); in tCK_to_ps()
452 ulong freq) in pctl_calc_timings() argument
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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mxs/
H A Dclock.h46 void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
47 void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
48 void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
49 void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq);
/rk3399_rockchip-uboot/board/freescale/t208xqds/
H A Dt208xqds.c33 static const char *freq[4] = { in checkboard() local
68 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6], in checkboard()
69 freq[(sw >> 4) & 0x3]); in checkboard()
70 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2], in checkboard()
71 freq[sw & 0x3]); in checkboard()
379 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); in get_board_sys_clk() local
383 val = freq * base; in get_board_sys_clk()
417 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); in get_board_ddr_clk() local
421 val = freq * base; in get_board_ddr_clk()
/rk3399_rockchip-uboot/board/freescale/t208xrdb/
H A Dt208xrdb.c28 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; in checkboard() local
52 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); in checkboard()
53 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]); in checkboard()
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mxs/
H A Dclock.c145 void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq) in mxs_set_ioclk() argument
152 if (freq == 0) in mxs_set_ioclk()
158 div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq; in mxs_set_ioclk()
199 void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) in mxs_set_sspclk() argument
220 if (freq > clk) in mxs_set_sspclk()
224 clk /= freq; in mxs_set_sspclk()
273 void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq) in mxs_set_ssp_busclock() argument
289 rate = sspclk / freq / divide; in mxs_set_ssp_busclock()
295 while (tgtclk > freq) { in mxs_set_ssp_busclock()
309 bus, tgtclk, freq); in mxs_set_ssp_busclock()
[all …]
/rk3399_rockchip-uboot/board/omicron/calimain/
H A Dcalimain.c85 int freq; in calimain_get_osc_freq() local
90 freq = 25000000; in calimain_get_osc_freq()
93 freq = 24000000; in calimain_get_osc_freq()
96 return freq; in calimain_get_osc_freq()
/rk3399_rockchip-uboot/board/freescale/corenet_ds/
H A Dcorenet_ds.c33 static const char * const freq[] = {"100", "125", "156.25", "212.5" }; in checkboard() local
65 printf("Bank%u=%sMhz ", i+1, freq[clock]); in checkboard()
70 printf("Bank4=%sMhz ", freq[sw & 3]); in checkboard()
78 printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); in checkboard()
79 printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); in checkboard()
80 printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); in checkboard()
/rk3399_rockchip-uboot/arch/arm/cpu/arm1136/mx31/
H A Dgeneric.c53 u32 freq = mx31_get_mcu_main_clk(); in mx31_get_ipg_clk() local
56 freq /= GET_PDR0_MAX_PODF(pdr0) + 1; in mx31_get_ipg_clk()
57 freq /= GET_PDR0_IPG_PODF(pdr0) + 1; in mx31_get_ipg_clk()
59 return freq; in mx31_get_ipg_clk()
65 u32 freq = mx31_get_mcu_main_clk(); in mx31_get_hsp_clk() local
68 freq /= GET_PDR0_HSP_PODF(pdr0) + 1; in mx31_get_hsp_clk()
70 return freq; in mx31_get_hsp_clk()
/rk3399_rockchip-uboot/tools/omap/
H A Dclocks_get_m_n.c52 u32 freq = target_freq_khz; in get_m_n_optimized() local
60 freq = ref_freq_khz * 2 * m / n; in get_m_n_optimized()
61 if (freq > target_freq_khz) { in get_m_n_optimized()
62 freq = freq_old; in get_m_n_optimized()
67 freq_old = freq; in get_m_n_optimized()
69 if (freq > freq_optimal) { in get_m_n_optimized()
70 freq_optimal = freq; in get_m_n_optimized()

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