283 	u64 freq;  in mxc_get_pll_pfd()  local
294 		freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);  in mxc_get_pll_pfd()
298 		freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);  in mxc_get_pll_pfd()
305 	return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>  in mxc_get_pll_pfd()
311 	u32 reg, freq;  in get_mcu_main_clk()  local
316 	freq = decode_pll(PLL_SYS, MXC_HCLK);  in get_mcu_main_clk()
318 	return freq / (reg + 1);  in get_mcu_main_clk()
323 	u32 reg, div = 0, freq = 0;  in get_periph_clk()  local
335 			freq = decode_pll(PLL_USBOTG, MXC_HCLK);  in get_periph_clk()
339 			freq = MXC_HCLK;  in get_periph_clk()
351 			freq = decode_pll(PLL_BUS, MXC_HCLK);  in get_periph_clk()
354 			freq = mxc_get_pll_pfd(PLL_BUS, 2);  in get_periph_clk()
357 			freq = mxc_get_pll_pfd(PLL_BUS, 0);  in get_periph_clk()
361 			freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;  in get_periph_clk()
368 	return freq / (div + 1);  in get_periph_clk()
401 	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */  in get_uart_clk()  local
407 			freq = MXC_HCLK;  in get_uart_clk()
413 	return freq / (uart_podf + 1);  in get_uart_clk()
485 	u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;  in get_mmdc_ch0_clk()  local
496 					freq = MXC_HCLK;  in get_mmdc_ch0_clk()
498 					freq = decode_pll(PLL_USBOTG, MXC_HCLK);  in get_mmdc_ch0_clk()
501 					freq = decode_pll(PLL_BUS, MXC_HCLK);  in get_mmdc_ch0_clk()
503 					freq = decode_pll(PLL_USBOTG, MXC_HCLK);  in get_mmdc_ch0_clk()
511 				freq = decode_pll(PLL_BUS, MXC_HCLK);  in get_mmdc_ch0_clk()
514 				freq = mxc_get_pll_pfd(PLL_BUS, 2);  in get_mmdc_ch0_clk()
517 				freq = mxc_get_pll_pfd(PLL_BUS, 0);  in get_mmdc_ch0_clk()
521 					freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;  in get_mmdc_ch0_clk()
538 				freq = decode_pll(PLL_AUDIO, MXC_HCLK) /  in get_mmdc_ch0_clk()
543 		return freq / (podf + 1) / (per2_clk2_podf + 1);  in get_mmdc_ch0_clk()
618 void mxs_set_lcdclk(u32 base_addr, u32 freq)  in mxs_set_lcdclk()  argument
629 	debug("mxs_set_lcdclk, freq = %dKHz\n", freq);  in mxs_set_lcdclk()
653 	temp = freq * max_pred * max_postd;  in mxs_set_lcdclk()
666 				freq *= post_div;  in mxs_set_lcdclk()
672 			printf("Fail to set rate to %dkhz", freq);  in mxs_set_lcdclk()
680 			temp = freq * i * j;  in mxs_set_lcdclk()
692 		printf("Fail to set rate to %dKHz", freq);  in mxs_set_lcdclk()
906 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)  in enable_fec_anatop_clock()  argument
914 	if (freq < ENET_25MHZ || freq > ENET_125MHZ)  in enable_fec_anatop_clock()
921 		reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);  in enable_fec_anatop_clock()
927 		reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);  in enable_fec_anatop_clock()
1270 	u32 freq;  in do_mx6_showclocks()  local
1271 	freq = decode_pll(PLL_SYS, MXC_HCLK);  in do_mx6_showclocks()
1272 	printf("PLL_SYS    %8d MHz\n", freq / 1000000);  in do_mx6_showclocks()
1273 	freq = decode_pll(PLL_BUS, MXC_HCLK);  in do_mx6_showclocks()
1274 	printf("PLL_BUS    %8d MHz\n", freq / 1000000);  in do_mx6_showclocks()
1275 	freq = decode_pll(PLL_USBOTG, MXC_HCLK);  in do_mx6_showclocks()
1276 	printf("PLL_OTG    %8d MHz\n", freq / 1000000);  in do_mx6_showclocks()
1277 	freq = decode_pll(PLL_ENET, MXC_HCLK);  in do_mx6_showclocks()
1278 	printf("PLL_NET    %8d MHz\n", freq / 1000000);  in do_mx6_showclocks()