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/rk3399_rockchip-uboot/arch/arm/dts/
H A Ddm816x-clocks.dtsi99 compatible = "ti,divider-clock";
117 compatible = "ti,divider-clock";
125 compatible = "ti,divider-clock";
133 compatible = "ti,divider-clock";
141 compatible = "ti,divider-clock";
149 compatible = "ti,divider-clock";
157 compatible = "ti,divider-clock";
165 compatible = "ti,divider-clock";
173 compatible = "ti,divider-clock";
189 compatible = "ti,divider-clock";
H A Ddra7xx-clocks.dtsi214 compatible = "ti,divider-clock";
225 compatible = "ti,divider-clock";
234 compatible = "ti,divider-clock";
245 compatible = "ti,divider-clock";
277 compatible = "ti,divider-clock";
303 compatible = "ti,divider-clock";
345 compatible = "ti,divider-clock";
379 compatible = "ti,divider-clock";
413 compatible = "ti,divider-clock";
424 compatible = "ti,divider-clock";
[all …]
H A Dam33xx-clocks.dtsi181 compatible = "ti,divider-clock";
190 compatible = "ti,divider-clock";
199 compatible = "ti,divider-clock";
215 compatible = "ti,divider-clock";
231 compatible = "ti,divider-clock";
255 compatible = "ti,divider-clock";
272 compatible = "ti,divider-clock";
558 compatible = "ti,divider-clock";
573 compatible = "ti,divider-clock";
614 compatible = "ti,divider-clock";
[all …]
H A Dam43xx-clocks.dtsi213 compatible = "ti,divider-clock";
224 compatible = "ti,divider-clock";
235 compatible = "ti,divider-clock";
253 compatible = "ti,divider-clock";
271 compatible = "ti,divider-clock";
289 compatible = "ti,divider-clock";
308 compatible = "ti,divider-clock";
568 compatible = "ti,divider-clock";
591 compatible = "ti,divider-clock";
667 compatible = "ti,divider-clock";
[all …]
H A Domap3xxx-clocks.dtsi26 compatible = "ti,divider-clock";
205 compatible = "ti,divider-clock";
246 compatible = "ti,divider-clock";
293 compatible = "ti,divider-clock";
311 compatible = "ti,divider-clock";
336 compatible = "ti,divider-clock";
361 compatible = "ti,divider-clock";
420 compatible = "ti,divider-clock";
448 compatible = "ti,divider-clock";
476 compatible = "ti,divider-clock";
[all …]
H A Dkeystone-k2e-clocks.dtsi17 reg-names = "control", "multiplier", "post-divider";
H A Domap34xx-omap36xx-clocks.dtsi158 compatible = "ti,divider-clock";
178 compatible = "ti,divider-clock";
H A Dsocfpga.dtsi277 fixed-divider = <4>;
284 fixed-divider = <2>;
298 fixed-divider = <1>;
458 fixed-divider = <4>;
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dclock.c249 u64 divider = parent_rate * 2; in clk_get_divider() local
252 divider += rate - 1; in clk_get_divider()
253 do_div(divider, rate); in clk_get_divider()
255 if ((s64)divider - 2 < 0) in clk_get_divider()
258 if ((s64)divider - 2 >= max_divider) in clk_get_divider()
261 return divider - 2; in clk_get_divider()
301 int divider) in get_rate_from_divider() argument
306 do_div(rate, divider + 2); in get_rate_from_divider()
379 int divider = clk_get_divider(divider_bits, divided_parent, in find_best_divider() local
382 divider); in find_best_divider()
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xx/
H A Dspeed.c23 uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2); in get_clocks() local
41 gd->arch.brg_clk = gd->cpu_clk / divider; in get_clocks()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf532x/
H A Dspeed.c55 int divider; in get_sys_clock() local
59 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
61 return (FREF / (3 * (1 << divider))); in get_sys_clock()
64 return (FREF / (2 << divider)); in get_sys_clock()
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A DKconfig298 int "Platform clock divider"
303 This is the divider that is used to derive Platform clock from
308 int "DSPI clock divider"
312 This is the divider that is used to derive DSPI clock from Platform
316 int "DUART clock divider"
320 This is the divider that is used to derive DUART clock from Platform
324 int "I2C clock divider"
328 This is the divider that is used to derive I2C clock from Platform
332 int "IFC clock divider"
336 This is the divider that is used to derive IFC clock from Platform
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mxs/
H A Dspl_mem_init.c148 const unsigned char divider = 33; in mxs_mem_init_clock() local
151 const unsigned char divider = 21; in mxs_mem_init_clock() local
161 writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), in mxs_mem_init_clock()
/rk3399_rockchip-uboot/drivers/serial/
H A Dserial_bcm283x_mu.c60 u32 divider; in bcm283x_mu_serial_setbrg() local
65 divider = plat->clock / (baudrate * 8); in bcm283x_mu_serial_setbrg()
68 writel(divider - 1, &regs->baud); in bcm283x_mu_serial_setbrg()
H A Dserial_pxa.c62 uint32_t divider = pxa_uart_get_baud_divider(baudrate); in pxa_setbrg_common() local
63 if (!divider) in pxa_setbrg_common()
75 writel(divider & 0xff, &uart_regs->dll); in pxa_setbrg_common()
76 writel(divider >> 8, &uart_regs->dlh); in pxa_setbrg_common()
H A Dserial_pl01x.c150 unsigned int divider; in pl01x_generic_setbrg() local
162 divider = clock / temp; in pl01x_generic_setbrg()
167 writel(divider, &regs->pl011_ibrd); in pl01x_generic_setbrg()
/rk3399_rockchip-uboot/drivers/mmc/
H A Dmxcmmc.c423 unsigned int divider; in mxcmci_set_clk_rate() local
428 for (divider = 1; divider <= 0xF; divider++) { in mxcmci_set_clk_rate()
431 x = (clk_in / (divider + 1)); in mxcmci_set_clk_rate()
439 if (divider < 0x10) in mxcmci_set_clk_rate()
448 writel((prescaler << 4) | divider, &host->base->clk_rate); in mxcmci_set_clk_rate()
/rk3399_rockchip-uboot/drivers/i2c/
H A Dfsl_i2c.c85 unsigned short divider; member
122 unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX); in set_i2c_bus_speed() local
144 speed = i2c_clk / divider; /* Fake something */ in set_i2c_bus_speed()
155 if ((c_div > divider) && (c_div < est_div)) { in set_i2c_bus_speed()
177 debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr); in set_i2c_bus_speed()
186 if (fsl_i2c_speed_map[i].divider >= divider) { in set_i2c_bus_speed()
190 speed = i2c_clk / fsl_i2c_speed_map[i].divider; in set_i2c_bus_speed()
H A Dast_i2c.c308 ulong i2c_rate, divider; in ast_i2c_set_speed() local
317 divider = i2c_rate / speed; in ast_i2c_set_speed()
331 writel(get_clk_reg_val(divider), &regs->cactcr1); in ast_i2c_set_speed()
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Dmicrochip,pic32-clock.txt4 multiplexers and few divider modules capable of supplying clocks
/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_a38x.c591 u32 divider = 0; in ddr3_tip_a38x_set_divider() local
605 divider = a38x_vco_freq_per_sar[sar_val] / freq_val[frequency]; in ddr3_tip_a38x_set_divider()
633 (divider << 8), (0x3f << 8))); in ddr3_tip_a38x_set_divider()
/rk3399_rockchip-uboot/board/freescale/s32v234evb/
H A Dclock.c166 static void aux_div_clk_config(uintptr_t cgm_addr, u8 ac, u8 dc, u32 divider) in aux_div_clk_config() argument
169 writel(MC_CGM_ACn_DCm_DE | MC_CGM_ACn_DCm_PREDIV(divider), in aux_div_clk_config()
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Dclocks-common.c270 u32 ddr_clk, sys_clk_khz, omap_rev, divider; in omap_ddr_clk() local
289 divider = 4; in omap_ddr_clk()
295 divider = 2; in omap_ddr_clk()
298 ddr_clk = ddr_clk / divider / core_dpll_params->m2; in omap_ddr_clk()
/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_spd.c188 static u32 ddr3_div(u32 val, u32 divider, u32 sub);
1251 u32 ddr3_div(u32 val, u32 divider, u32 sub) argument
1253 return val / divider + (val % divider > 0 ? 1 : 0) - sub;
/rk3399_rockchip-uboot/doc/device-tree-bindings/leds/
H A Dleds-bcm6358.txt16 - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8.

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