249 	u64 divider = parent_rate * 2;  in clk_get_divider()  local
252 	divider += rate - 1;  in clk_get_divider()
253 	do_div(divider, rate);  in clk_get_divider()
255 	if ((s64)divider - 2 < 0)  in clk_get_divider()
258 	if ((s64)divider - 2 >= max_divider)  in clk_get_divider()
261 	return divider - 2;  in clk_get_divider()
301 					   int divider)  in get_rate_from_divider()  argument
306 	do_div(rate, divider + 2);  in get_rate_from_divider()
379 		int divider = clk_get_divider(divider_bits, divided_parent,  in find_best_divider()  local
382 						divider);  in find_best_divider()
386 		if (divider != -1 && error < best_error) {  in find_best_divider()
389 			best_divider = divider;  in find_best_divider()
408 				int mux_bits, unsigned divider)  in adjust_periph_pll()  argument
413 			divider << OUT_CLK_DIVISOR_SHIFT);  in adjust_periph_pll()
445 	int divider;  in clock_adjust_periph_pll_div()  local
452 	divider = find_best_divider(divider_bits, pll_rate[parent],  in clock_adjust_periph_pll_div()
457 	assert(divider >= 0);  in clock_adjust_periph_pll_div()
458 	if (adjust_periph_pll(periph_id, source, mux_bits, divider))  in clock_adjust_periph_pll_div()