| /rk3399_rockchip-uboot/cmd/ |
| H A D | universe.c | 80 writel(0x00800000, &dev->uregs->lsi[j].ctl); in universe_init()
81 writel(0x00800000, &dev->uregs->vsi[j].ctl); in universe_init()
123 unsigned int ctl = 0; in universe_pci_slave_window() local
131 if (0x00800000 == readl(&dev->uregs->lsi[i].ctl)) in universe_pci_slave_window()
149 ctl = 0x00000000; in universe_pci_slave_window()
152 ctl = 0x00010000; in universe_pci_slave_window()
155 ctl = 0x00020000; in universe_pci_slave_window()
161 ctl |= 0x00000000; in universe_pci_slave_window()
164 ctl |= 0x00008000; in universe_pci_slave_window()
169 ctl |= 0x00001000; in universe_pci_slave_window()
[all …]
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| H A D | tsi148.c | 136 unsigned int ctl = 0; in tsi148_pci_slave_window() local
167 ctl = 0x00000000; in tsi148_pci_slave_window()
170 ctl = 0x00000001; in tsi148_pci_slave_window()
173 ctl = 0x00000002; in tsi148_pci_slave_window()
179 ctl |= 0x00000000; in tsi148_pci_slave_window()
182 ctl |= 0x00000010; in tsi148_pci_slave_window()
187 ctl |= 0x00000020; in tsi148_pci_slave_window()
191 ctl |= 0x00000000; in tsi148_pci_slave_window()
194 ctl |= 0x00000040; in tsi148_pci_slave_window()
198 ctl |= 0x80040000; /* enable, no prefetch */ in tsi148_pci_slave_window()
[all …]
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| /rk3399_rockchip-uboot/drivers/gpio/ |
| H A D | stm32_gpio.c | 45 const struct stm32_gpio_ctl *ctl) in stm32_gpio_config() argument
55 if (CHECK_CTL(ctl)) { in stm32_gpio_config()
63 clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i); in stm32_gpio_config()
67 clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i); in stm32_gpio_config()
68 clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i); in stm32_gpio_config()
69 clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i); in stm32_gpio_config()
70 clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i); in stm32_gpio_config()
130 struct stm32_gpio_ctl ctl; in gpio_direction_input() local
134 ctl.af = STM32_GPIO_AF0; in gpio_direction_input()
135 ctl.mode = STM32_GPIO_MODE_IN; in gpio_direction_input()
[all …]
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| /rk3399_rockchip-uboot/drivers/i2c/ |
| H A D | adi_i2c.c | 90 u16 int_stat, ctl; in wait_for_completion() local
105 ctl = readw(&twi->master_ctl); in wait_for_completion()
107 writew(ctl | RSTART | MDIR, in wait_for_completion()
110 writew(ctl | STOP, &twi->master_ctl); in wait_for_completion()
119 ctl = readw(&twi->master_ctl); in wait_for_completion()
120 writew(ctl | STOP, &twi->master_ctl); in wait_for_completion()
130 ctl = readw(&twi->master_ctl); in wait_for_completion()
131 ctl = (ctl & ~RSTART) | in wait_for_completion()
133 writew(ctl, &twi->master_ctl); in wait_for_completion()
152 u16 ctl; in i2c_transfer() local
[all …]
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| /rk3399_rockchip-uboot/arch/arm/mach-imx/ |
| H A D | cpu.c | 93 uint32_t ctl; member
102 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
103 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
104 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
105 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
117 unsigned ctl = readl(&mem->ctl); in imx_ddr_size() local
121 bits += ESD_MMDC_CTL_GET_ROW(ctl); in imx_ddr_size()
122 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)]; in imx_ddr_size()
124 bits += ESD_MMDC_CTL_GET_WIDTH(ctl); in imx_ddr_size()
125 bits += ESD_MMDC_CTL_GET_CS1(ctl); in imx_ddr_size()
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| /rk3399_rockchip-uboot/drivers/pinctrl/ |
| H A D | pinctrl_stm32.c | 18 const struct stm32_gpio_ctl *ctl) in stm32_gpio_config() argument
24 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || in stm32_gpio_config()
25 ctl->pupd > 2 || ctl->speed > 3) in stm32_gpio_config()
30 ctl->af << index); in stm32_gpio_config()
34 ctl->mode << index); in stm32_gpio_config()
36 ctl->speed << index); in stm32_gpio_config()
37 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index); in stm32_gpio_config()
40 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index); in stm32_gpio_config()
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| /rk3399_rockchip-uboot/drivers/net/phy/ |
| H A D | et1011c.c | 30 int ctl = 0; in et1011c_config() local
31 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
32 if (ctl < 0) in et1011c_config()
33 return ctl; in et1011c_config()
34 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | in et1011c_config()
37 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
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| H A D | phy.c | 131 int ctl = BMCR_ANRESTART; in genphy_setup_forced() local
136 ctl |= BMCR_SPEED1000; in genphy_setup_forced()
138 ctl |= BMCR_SPEED100; in genphy_setup_forced()
141 ctl |= BMCR_FULLDPLX; in genphy_setup_forced()
143 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_setup_forced()
155 int ctl; in genphy_restart_aneg() local
157 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_restart_aneg()
159 if (ctl < 0) in genphy_restart_aneg()
160 return ctl; in genphy_restart_aneg()
162 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); in genphy_restart_aneg()
[all …]
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| /rk3399_rockchip-uboot/drivers/reset/ |
| H A D | sandbox-reset-test.c | 14 struct reset_ctl ctl; member
22 return reset_get_by_name(dev, "test", &sbrt->ctl); in sandbox_reset_test_get()
36 return reset_assert(&sbrt->ctl); in sandbox_reset_test_assert()
50 return reset_deassert(&sbrt->ctl); in sandbox_reset_test_deassert()
64 return reset_free(&sbrt->ctl); in sandbox_reset_test_free()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | timer.h | 21 u32 ctl; member
29 u32 ctl; /* 0x80 */ member
37 u32 ctl; /* 0xa0 */ member
44 u32 ctl; /* 0x100 */ member
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| H A D | watchdog.h | 25 u32 ctl; /* 0x00 */ member
39 u32 ctl; /* 0x10 */ member
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| H A D | dma_sun4i.h | 12 u32 ctl; /* 0x00 Control */ member
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| /rk3399_rockchip-uboot/drivers/net/ |
| H A D | at91_emac.c | 93 writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); in at91emac_EnableMDIO()
99 writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); in at91emac_DisableMDIO()
351 writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); in at91emac_init()
373 writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE, in at91emac_init()
374 &emac->ctl); in at91emac_init()
388 writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE), in at91emac_halt()
389 &emac->ctl); in at91emac_halt()
443 writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl); in at91emac_recv()
444 writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl); in at91emac_recv()
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| H A D | xilinx_ll_temac_mdio.c | 78 out_be32(®s->ctl, TEMAC_MIIMAI); in ll_temac_local_mdio_read()
95 out_be32(®s->ctl, CTL_WEN | TEMAC_MIIMWD); in ll_temac_local_mdio_write()
100 out_be32(®s->ctl, CTL_WEN | TEMAC_MIIMAI); in ll_temac_local_mdio_write()
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| H A D | sunxi_emac.c | 21 u32 ctl; /* 0x00 */ member
323 writel(0, ®s->ctl); in emac_reset()
326 writel(1, ®s->ctl); in emac_reset()
402 setbits_le32(®s->ctl, 0x7); in _sunxi_emac_eth_init()
433 clrbits_le32(®s->ctl, 0x1 << 2); in _sunxi_emac_eth_recv()
441 setbits_le32(®s->ctl, 0x1 << 2); in _sunxi_emac_eth_recv()
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| /rk3399_rockchip-uboot/arch/mips/mach-ath79/ar934x/ |
| H A D | ddr.c | 43 u32 reg, cycle, ctl; in ar934x_ddr_init() local
56 ctl = BIT(6); /* Undocumented bit :-( */ in ar934x_ddr_init()
63 ctl = 0; in ar934x_ddr_init()
76 writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF); in ar934x_ddr_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-keystone/ |
| H A D | clock.c | 54 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | in bypass_main_pll()
112 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); in configure_main_pll()
116 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK); in configure_main_pll()
152 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK); in configure_main_pll()
154 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK); in configure_main_pll()
159 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK); in configure_main_pll()
288 if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) { in pll_freq_get()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx25/ |
| H A D | macro.h | 85 .macro init_m3if ctl=0x00000001
87 write32 IMX_M3IF_CTRL_BASE, \ctl
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| /rk3399_rockchip-uboot/drivers/ata/ |
| H A D | sata_dwc.c | 53 struct dmareg ctl; member
306 ap.ctl = ATA_DEVCTL_OBS; in init_sata()
467 writeb(ap->ctl, ioaddr->ctl_addr); in sata_dwc_softreset()
471 writeb(ap->ctl | ATA_SRST, ioaddr->ctl_addr); in sata_dwc_softreset()
474 writeb(ap->ctl, ioaddr->ctl_addr); in sata_dwc_softreset()
751 tf.ctl = ap->ctl; in ata_dev_read_id()
946 qc->tf.ctl = 0; in ata_qc_reinit()
1157 qc->tf.ctl |= ATA_NIEN; in ata_qc_issue_prot()
1188 if (tf->ctl != ap->last_ctl) { in ata_tf_load()
1190 writeb(tf->ctl, ioaddr->ctl_addr); in ata_tf_load()
[all …]
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-armv7/ |
| H A D | globaltimer.h | 13 u32 ctl; member
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx35/ |
| H A D | lowlevel_macro.S | 93 .macro init_m3if ctl=0x00000040 argument
95 write32 M3IF_BASE_ADDR, \ctl
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| /rk3399_rockchip-uboot/arch/arm/mach-rmobile/ |
| H A D | timer.c | 56 writel(0x01, &global_timer->ctl); in timer_init()
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| /rk3399_rockchip-uboot/drivers/mtd/spi/ |
| H A D | spi_flash.c | 553 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) in sst26_process_bpr() argument
555 switch (ctl) { in sst26_process_bpr()
585 static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum lock_ctl ctl) in sst26_lock_ctl() argument
625 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) in sst26_lock_ctl()
637 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) in sst26_lock_ctl()
644 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) in sst26_lock_ctl()
652 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) in sst26_lock_ctl()
662 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) in sst26_lock_ctl()
670 if (ctl == SST26_CTL_CHECK) in sst26_lock_ctl()
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| /rk3399_rockchip-uboot/drivers/timer/ |
| H A D | sti-timer.c | 56 writel(0x01, &priv->global_timer->ctl); in sti_timer_probe()
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | board.c | 285 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); in reset_cpu()
298 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); in reset_cpu()
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