1*a19e735dSRoy Spliet /* 2*a19e735dSRoy Spliet * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com> 3*a19e735dSRoy Spliet * 4*a19e735dSRoy Spliet * SPDX-License-Identifier: GPL-2.0+ 5*a19e735dSRoy Spliet */ 6*a19e735dSRoy Spliet 7*a19e735dSRoy Spliet #ifndef _SUNXI_DMA_SUN4I_H 8*a19e735dSRoy Spliet #define _SUNXI_DMA_SUN4I_H 9*a19e735dSRoy Spliet 10*a19e735dSRoy Spliet struct sunxi_dma_cfg 11*a19e735dSRoy Spliet { 12*a19e735dSRoy Spliet u32 ctl; /* 0x00 Control */ 13*a19e735dSRoy Spliet u32 src_addr; /* 0x04 Source address */ 14*a19e735dSRoy Spliet u32 dst_addr; /* 0x08 Destination address */ 15*a19e735dSRoy Spliet u32 bc; /* 0x0C Byte counter */ 16*a19e735dSRoy Spliet u32 res0[2]; 17*a19e735dSRoy Spliet u32 ddma_para; /* 0x18 extra parameter (dedicated DMA only) */ 18*a19e735dSRoy Spliet u32 res1; 19*a19e735dSRoy Spliet }; 20*a19e735dSRoy Spliet 21*a19e735dSRoy Spliet struct sunxi_dma 22*a19e735dSRoy Spliet { 23*a19e735dSRoy Spliet u32 irq_en; /* 0x000 IRQ enable */ 24*a19e735dSRoy Spliet u32 irq_pend; /* 0x004 IRQ pending */ 25*a19e735dSRoy Spliet u32 auto_gate; /* 0x008 auto gating */ 26*a19e735dSRoy Spliet u32 res0[61]; 27*a19e735dSRoy Spliet struct sunxi_dma_cfg ndma[8]; /* 0x100 Normal DMA */ 28*a19e735dSRoy Spliet u32 res1[64]; 29*a19e735dSRoy Spliet struct sunxi_dma_cfg ddma[8]; /* 0x300 Dedicated DMA */ 30*a19e735dSRoy Spliet }; 31*a19e735dSRoy Spliet 32*a19e735dSRoy Spliet enum ddma_drq_type { 33*a19e735dSRoy Spliet DDMA_DST_DRQ_SRAM = 0, 34*a19e735dSRoy Spliet DDMA_SRC_DRQ_SRAM = 0, 35*a19e735dSRoy Spliet DDMA_DST_DRQ_SDRAM = 1, 36*a19e735dSRoy Spliet DDMA_SRC_DRQ_SDRAM = 1, 37*a19e735dSRoy Spliet DDMA_DST_DRQ_PATA = 2, 38*a19e735dSRoy Spliet DDMA_SRC_DRQ_PATA = 2, 39*a19e735dSRoy Spliet DDMA_DST_DRQ_NAND = 3, 40*a19e735dSRoy Spliet DDMA_SRC_DRQ_NAND = 3, 41*a19e735dSRoy Spliet DDMA_DST_DRQ_USB0 = 4, 42*a19e735dSRoy Spliet DDMA_SRC_DRQ_USB0 = 4, 43*a19e735dSRoy Spliet DDMA_DST_DRQ_ETHERNET_MAC_TX = 6, 44*a19e735dSRoy Spliet DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7, 45*a19e735dSRoy Spliet DDMA_DST_DRQ_SPI1_TX = 8, 46*a19e735dSRoy Spliet DDMA_SRC_DRQ_SPI1_RX = 9, 47*a19e735dSRoy Spliet DDMA_DST_DRQ_SECURITY_SYS_TX = 10, 48*a19e735dSRoy Spliet DDMA_SRC_DRQ_SECURITY_SYS_RX = 11, 49*a19e735dSRoy Spliet DDMA_DST_DRQ_TCON0 = 14, 50*a19e735dSRoy Spliet DDMA_DST_DRQ_TCON1 = 15, 51*a19e735dSRoy Spliet DDMA_DST_DRQ_MSC = 23, 52*a19e735dSRoy Spliet DDMA_SRC_DRQ_MSC = 23, 53*a19e735dSRoy Spliet DDMA_DST_DRQ_SPI0_TX = 26, 54*a19e735dSRoy Spliet DDMA_SRC_DRQ_SPI0_RX = 27, 55*a19e735dSRoy Spliet DDMA_DST_DRQ_SPI2_TX = 28, 56*a19e735dSRoy Spliet DDMA_SRC_DRQ_SPI2_RX = 29, 57*a19e735dSRoy Spliet DDMA_DST_DRQ_SPI3_TX = 30, 58*a19e735dSRoy Spliet DDMA_SRC_DRQ_SPI3_RX = 31, 59*a19e735dSRoy Spliet }; 60*a19e735dSRoy Spliet 61*a19e735dSRoy Spliet #define SUNXI_DMA_CTL_SRC_DRQ(a) ((a) & 0x1f) 62*a19e735dSRoy Spliet #define SUNXI_DMA_CTL_MODE_IO (1 << 5) 63*a19e735dSRoy Spliet #define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 (2 << 9) 64*a19e735dSRoy Spliet #define SUNXI_DMA_CTL_DST_DRQ(a) (((a) & 0x1f) << 16) 65*a19e735dSRoy Spliet #define SUNXI_DMA_CTL_DST_DATA_WIDTH_32 (2 << 25) 66*a19e735dSRoy Spliet #define SUNXI_DMA_CTL_TRIGGER (1 << 31) 67*a19e735dSRoy Spliet 68*a19e735dSRoy Spliet #endif /* _SUNXI_DMA_SUN4I_H */ 69