UPSTREAM: sf: Add a method to obtain the block-protect setting

It is useful to obtain the block-protect setting of the SPI flash, so we
know whether it is fully open or (perhaps partially) write-pro

UPSTREAM: sf: Add a method to obtain the block-protect setting

It is useful to obtain the block-protect setting of the SPI flash, so we
know whether it is fully open or (perhaps partially) write-protected. Add
a method for this. Update the sandbox driver to process this operation and
add a test.

Signed-off-by: Simon Glass <sjg@chromium.org
Change-Id: I8e8abe197ab483a26622f02666cc234a1544e642
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a58986ca8b53d8c7a441397082f84edc7f47d19f)

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UPSTREAM: sf: Add MICRON manufacturer id

NOR flash name MT35X_QLKA and MT25Q_** used on NXP board has
manufacturer id as 0x2C, which are rather for newer flashes
after the split of Micron from ST.

UPSTREAM: sf: Add MICRON manufacturer id

NOR flash name MT35X_QLKA and MT25Q_** used on NXP board has
manufacturer id as 0x2C, which are rather for newer flashes
after the split of Micron from ST.

So macro for this micron manufacturer id.

Change-Id: Ib32d4350646f2d2946fee85dd59e55a72a55627f
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
[jagan: updated commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5c391486b411025785e064f160d248bef31b3d28)

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UPSTREAM: dm: spi: Add logging of some return values

When SPI flash operations fail it is helpful to be able to see the error
codes and where they are generated. Add logging to capture this
informat

UPSTREAM: dm: spi: Add logging of some return values

When SPI flash operations fail it is helpful to be able to see the error
codes and where they are generated. Add logging to capture this
information for read operations.

Change-Id: I58270e564a558fbaf9ae2c5b0d888d3af842e09c
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5e24a2ef8bf4f09b18cf4e943c73bfdd169a7581)

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UPSTREAM: sf: Avoid allocating memory on every read operation

At present spi_flash_cmd_read_ops() allocates and frees a few bytes of
memory every time it is called. It is faster to use the stack for

UPSTREAM: sf: Avoid allocating memory on every read operation

At present spi_flash_cmd_read_ops() allocates and frees a few bytes of
memory every time it is called. It is faster to use the stack for this
and this is now supported by the minimum GCC version required by U-Boot.

Remove the allocation and use a variable-sized array instead.

Change-Id: I1c59601b4d56cd941784cbdac830a562c1491bbd
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 97f57109bb750d0b2908d6ecd4aef3801baf1cf2)

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UPSTREAM: sf: Set current flash bank to 0 in clean_bar()

The clean_bar() function resets the SPI NOR BAR register to 0, but
does not set the flash->curr_bar to 0 , therefore those two can get
out of

UPSTREAM: sf: Set current flash bank to 0 in clean_bar()

The clean_bar() function resets the SPI NOR BAR register to 0, but
does not set the flash->curr_bar to 0 , therefore those two can get
out of sync, which could ultimatelly result in corrupted flash content.

The simplest test case is this:

=> mw 0x10000000 0x1234abcd 0x4000
=> sf probe
=> sf erase 0x1000000 0x10000
=> sf write 0x10000000 0x1000000 0x10000

=> sf probe ; sf read 0x12000000 0 0x10000 ; md 0x12000000

That is, erase a sector above the 16 MiB boundary and write it with
random pre-configured data. What will actually happen without this
patch is the sector will be erased, but the data will be written to
BAR 0 offset 0x0 in the flash.

This is because the erase command will call write_bar()+clean_bar(),
which will leave flash->bank_curr = 1 while the hardware BAR registers
will be set to 0 through clean_bar(). The subsequent write will also
trigger write_bar()+clean_bar(), but write_bar checks if the target
bank == flash->bank_curr and if so, does NOT reconfigure the BAR in
the SPI NOR. Since flash->bank_curr is still 1 and out of sync with
the HW, the condition matches, BAR programming is skipped and write
ends up at address 0x0, thus corrupting flash content.

Change-Id: Ib8ec33a2b890ee7f1566846172c51254b0388964
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8ff4130debcc09594b550209c44abf6c7e3ee595)

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UPSTREAM: sf: Default page size Spansion flash "S25FS512S" is 256b

page size for JEDEC EXT starting 0x4d00 is 512b,
except JEDEC ID 0x215, 0x216 and 0x220

Change-Id: I0f55264c67685f7b497cffc5250927

UPSTREAM: sf: Default page size Spansion flash "S25FS512S" is 256b

page size for JEDEC EXT starting 0x4d00 is 512b,
except JEDEC ID 0x215, 0x216 and 0x220

Change-Id: I0f55264c67685f7b497cffc52509277678daccde
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
[jagan: added proper commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4eaa2fa16968359ffcf207e63848ed7f3a6e4309)

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UPSTREAM: mtd: sf: Add support of sst26wf* flash ICs protection ops

sst26wf flash series block protection implementation differs
from other SST series, so add specific implementation
flash_lock/flas

UPSTREAM: mtd: sf: Add support of sst26wf* flash ICs protection ops

sst26wf flash series block protection implementation differs
from other SST series, so add specific implementation
flash_lock/flash_unlock/flash_is_locked functions for sst26wf
flash ICs.

Change-Id: Id4228dde75de212d7b29dc2a621f64805fed5b48
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 3d4fed87a5fa3ffedf64ff2811cd95c5ac4503ac)

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UPSTREAM: spi: spi_flash: do not fail silently on bad user input

Make sure the user is notified instead of silently returning an error.

Change-Id: I727948d67e404a09a2b444296a3cd8189a3662ed
Signed-o

UPSTREAM: spi: spi_flash: do not fail silently on bad user input

Make sure the user is notified instead of silently returning an error.

Change-Id: I727948d67e404a09a2b444296a3cd8189a3662ed
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit aa1ced7f09798700f3d96f39f6f5dc7d3d34cf66)

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UPSTREAM: drivers: spi: consider command bytes when sending transfers

Command bytes are part of the written bytes and they should be taken into
account when sending a spi transfer.

Change-Id: I8b38

UPSTREAM: drivers: spi: consider command bytes when sending transfers

Command bytes are part of the written bytes and they should be taken into
account when sending a spi transfer.

Change-Id: I8b38a1c15cbfc5bc5394ca59e386ddff413210fc
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6c94bd12c4adca45033ef89daafa66fbfc9acd17)

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UPSTREAM: drivers: spi: allow limiting reads

For some SPI controllers it's not possible to keep the CS active between
transfers and they are limited to a known number of bytes.
This splits spi_flash

UPSTREAM: drivers: spi: allow limiting reads

For some SPI controllers it's not possible to keep the CS active between
transfers and they are limited to a known number of bytes.
This splits spi_flash reads into different iterations in order to respect
the SPI controller limits.

Change-Id: I9e5621b1939829ff8f9ed7d4dca50bb87d27b2ef
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8af74edc30bb60a90a5c4d2769ff3129b187796e)

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UPSTREAM: sf: bar: Clean BA24 Bank Address Register bit after read/write/erase operation

The content of Bank Address Register (BAR) is volatile. It is cleared
after power cycle or reset command (RES

UPSTREAM: sf: bar: Clean BA24 Bank Address Register bit after read/write/erase operation

The content of Bank Address Register (BAR) is volatile. It is cleared
after power cycle or reset command (RESET F0h).

Some memories (like e.g. s25fl256s) use it to access memory larger than
0x1000000 (16 MiB).

The problem shows up when one:

1. Reads/writes/erases memory > 16 MiB
2. Calls "reset" u-boot command (which is not causing BAR to be cleared)

In the above scenario, the SoC ROM sends 0x000000 address to read SPL.
Unfortunately, the BA24 bit is still set and hence it receives content
from 0x1000000 (16 MiB) memory address.
As a result the SoC aborts and we hang. Only power cycle can take the
SoC out of this state.

How to reproduce/test:

sf probe; sf erase 0x1200000 0x800000; reset
sf probe; sf erase 0x1200000 0x800000; sf write 0x11000000 0x1200000 0x800000; reset
sf probe; sf read 0x11000000 0x1200000 0x800000; reset

Change-Id: I9483ea18defb28635f951ff6a4c788f54859ac37
Signed-off-by: Lukasz Majewski <lukma@denx.de>
[Fixed comment text on clean_bar function]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ca1ac16da097bf0ab176b1a201653553160dc042)

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sf: add support for GD25Q256

Add support for GD25Q256, a 32MiB SPI Nor
flash from Gigadevice.

Change-Id: Id28c00189058971580406270e708a126c94c0461
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

Merge git://git.denx.de/u-boot-spi

sf: Preserve QE bit when clearing BP# bits for Macronix flash

On some flash (like Macronix), QE (quad enable) bit is in the same
status register as BP# bits, and we need preserve its original value

sf: Preserve QE bit when clearing BP# bits for Macronix flash

On some flash (like Macronix), QE (quad enable) bit is in the same
status register as BP# bits, and we need preserve its original value
during a reboot cycle as this is required by some platforms (like
Intel ICH SPI controller working under descriptor mode).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[Refined code for readability]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

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dm: spi-flash: Convert uclass to livetree

Update the SPI flash uclass to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>

Merge git://git.denx.de/u-boot-dm

dm: core: Replace of_offset with accessor

At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree,

dm: core: Replace of_offset with accessor

At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>

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Merge branch 'master' of git://git.denx.de/u-boot-spi

Revert "sf: Fix quad bit set for micron devices"

This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe.

Once the 'Quad Enable' bit is cleared in their Enhanced Volatile
Configuration Registe

Revert "sf: Fix quad bit set for micron devices"

This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe.

Once the 'Quad Enable' bit is cleared in their Enhanced Volatile
Configuration Register (EVCR), Micron memories expect ALL commands to use
the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer
accepted.

Within the reverted commit, the write_evcr() function is implemented using
the spi_flash_write_common(), which is a shortcut for the
[ spi_flash_cmd_write_enable(), spi_flash_cmd_write(),
spi_flash_cmd_wait_ready() ] sequence.

Since the internal state of the Micron memory has been changed when the
spi_flash_cmd_write() function completes, the later call of the
spi_flash_cmd_wait_ready() function fails.

Indeed the SPI controller driver is not aware of the SPI protocol switch.

Further patches will fix the support of Micron QSPI memories.

Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
[Rebase on master, use JEDEC_MFR(info) in place of idcode0]
Signed-off-by: Jagan Teki <jagan@openedev.com>

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sf: Do not force the DT memory map size to exactly match the device

As long as the memory mapped size specifeid in the DT is the same or
bigger than the device size, it will work. So do not force th

sf: Do not force the DT memory map size to exactly match the device

As long as the memory mapped size specifeid in the DT is the same or
bigger than the device size, it will work. So do not force the sizes
to be identical.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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mtd: spi: don't return -1 when scan succeed

In spi_flash_scan, 'ret' is initialled to -1, but 'ret' is not always
used to store a return value, in that case, even when the function
succeed, an error

mtd: spi: don't return -1 when scan succeed

In spi_flash_scan, 'ret' is initialled to -1, but 'ret' is not always
used to store a return value, in that case, even when the function
succeed, an error (-1) will be returned.
Lets just return 0 if we hit the end of the function.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Merge git://git.denx.de/u-boot-rockchip

spi: Add of-platdata support to SPI and SPI flash

Some boards may want to use these subsystems with of-platdata in SPL. Add
support for this by avoiding any device tree access in this case.

Signed-

spi: Add of-platdata support to SPI and SPI flash

Some boards may want to use these subsystems with of-platdata in SPL. Add
support for this by avoiding any device tree access in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>

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Merge branch 'master' of git://git.denx.de/u-boot-spi