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Searched refs:core (Results 1 – 25 of 195) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c165 .core = core_dpll_params_es1_1524mhz,
179 .core = core_dpll_params_es2_1600mhz_ddr200mhz,
193 .core = core_dpll_params_1600mhz,
207 .core = core_dpll_params_1600mhz,
221 .core = core_dpll_params_1600mhz,
270 .core.value[OPP_NOM] = 1200,
271 .core.addr = SMPS_REG_ADDR_VCORE3,
272 .core.pmic = &twl6030_4430es1,
284 .core.value[OPP_NOM] = 1200,
285 .core.addr = SMPS_REG_ADDR_VCORE3,
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/
H A Dpmu.c32 int core, cpu; in pmu_set_nominal() local
38 core = VDD_CORE_NOMINAL_T20; in pmu_set_nominal()
42 core = VDD_CORE_NOMINAL_T25; in pmu_set_nominal()
63 return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP, in pmu_set_nominal()
/rk3399_rockchip-uboot/drivers/misc/
H A Drockchip_pm_config.c40 struct rk_mcu_sleep_core_tag core; member
102 config->core.hdr.tag = RK_ATAG_MCU_SLP_CORE; in parse_mcu_sleep_config()
103 config->core.hdr.size = sizeof(struct rk_mcu_sleep_core_tag) / sizeof(u32); in parse_mcu_sleep_config()
104 config->core.total_size = sizeof(struct rk_mcu_sleep_tags) - in parse_mcu_sleep_config()
154 config->core.total_size += slp_tag->hdr.size * sizeof(u32); in parse_mcu_sleep_config()
167 config->core.total_size += sizeof(struct rk_sleep_tag); in parse_mcu_sleep_config()
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c211 .core = core_dpll_params_2128mhz_ddr532,
225 .core = core_dpll_params_2128mhz_ddr532_es2,
239 .core = core_dpll_params_2128mhz_dra7xx,
250 .core = core_dpll_params_2128mhz_dra7xx,
309 .core.value[OPP_NOM] = VDD_CORE,
310 .core.addr = SMPS_REG_ADDR_8_CORE,
311 .core.pmic = &palmas,
324 .core.value[OPP_NOM] = VDD_CORE_ES2,
325 .core.addr = SMPS_REG_ADDR_8_CORE,
326 .core.pmic = &palmas,
[all …]
/rk3399_rockchip-uboot/drivers/clk/renesas/
H A Dclk-rcar-gen3.c707 static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core) in gen3_clk_get_core() argument
720 *core = &priv->core_clk[i]; in gen3_clk_get_core()
729 const struct cpg_core_clk *core; in gen3_clk_get_parent() local
740 ret = gen3_clk_get_core(clk, &core); in gen3_clk_get_parent()
744 if (core->type == CLK_TYPE_IN) in gen3_clk_get_parent()
747 parent->id = core->parent; in gen3_clk_get_parent()
793 const struct cpg_core_clk *core; in gen3_clk_get_rate() local
814 ret = gen3_clk_get_core(clk, &core); in gen3_clk_get_rate()
818 switch (core->type) { in gen3_clk_get_rate()
820 if (core->id == CLK_EXTAL) { in gen3_clk_get_rate()
[all …]
/rk3399_rockchip-uboot/board/compulab/cl-som-am57x/
H A Dspl.c190 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
191 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
192 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
193 .core.addr = TPS659038_REG_ADDR_SMPS7,
194 .core.pmic = &tps659038,
/rk3399_rockchip-uboot/drivers/usb/gadget/udc/
H A DMakefile8 obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o
11 obj-$(CONFIG_$(SPL_)DM_USB_GADGET) += udc-core.o
/rk3399_rockchip-uboot/drivers/spi/
H A DKconfig33 IP core. Please find details on the "Embedded Peripherals IP
41 this Andestech IP core.
66 SPI core.
81 Broadcom SPI core.
88 Cadence IP core.
95 IP core.
102 Exynos IP core.
109 this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
117 ICH IP core.
124 Marvell IP core.
[all …]
/rk3399_rockchip-uboot/board/armltd/integrator/
H A DREADME14 Each may be fitted with a variety of core modules (CMs).
15 Each CM consists of a ARM processor core and associated hardware e.g
52 However, to avoid duplicating code through all processor files, a generic core
68 The U-Boot make targets map to the available core modules as below.
82 The final groups of targets are for core modules where no explicit cpu
84 using the generic "arm_intcm" core:
103 to indicate the core module & core configuration and ensure that
/rk3399_rockchip-uboot/board/ti/am57xx/
H A Dboard.c282 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
283 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
284 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
285 .core.addr = TPS659038_REG_ADDR_SMPS6,
286 .core.pmic = &tps659038,
330 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
331 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
332 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
333 .core.addr = TPS659038_REG_ADDR_SMPS7,
334 .core.pmic = &tps659038,
[all …]
/rk3399_rockchip-uboot/board/ti/dra7xx/
H A Devm.c341 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
342 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
343 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
344 .core.addr = TPS659038_REG_ADDR_SMPS7,
345 .core.pmic = &tps659038,
367 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
368 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
369 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
370 .core.addr = TPS65917_REG_ADDR_SMPS2,
371 .core.pmic = &tps659038,
[all …]
/rk3399_rockchip-uboot/drivers/mtd/spi/
H A DMakefile16 spi-nor-y += spi-nor-core.o
19 spi-nor-y += spi-nor-core.o
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dmp.c43 void wake_secondary_core_n(int cluster, int core, int cluster_cores) in wake_secondary_core_n() argument
49 mpidr = ((cluster << 8) | core); in wake_secondary_core_n()
56 rst->brrl |= 1 << ((cluster * cluster_cores) + core); in wake_secondary_core_n()
177 int is_core_valid(unsigned int core) in is_core_valid() argument
179 return !!((1 << core) & cpu_mask()); in is_core_valid()
H A Dcpu.h7 int fsl_qoriq_core_to_cluster(unsigned int core);
H A Dcpu.c348 int fsl_qoriq_core_to_cluster(unsigned int core) in fsl_qoriq_core_to_cluster() argument
361 if (count == core) in fsl_qoriq_core_to_cluster()
372 u32 fsl_qoriq_core_to_type(unsigned int core) in fsl_qoriq_core_to_type() argument
386 if (count == core) in fsl_qoriq_core_to_type()
412 unsigned int i, core; in print_cpuinfo() local
422 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { in print_cpuinfo()
425 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); in print_cpuinfo()
426 printf("CPU%d(%s):%-4s MHz ", core, in print_cpuinfo()
431 strmhz(buf, sysinfo.freq_processor[core])); in print_cpuinfo()
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/
H A Dmp.c72 int is_core_valid(unsigned int core) in is_core_valid() argument
76 if (core > nr_cores) in is_core_valid()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xxx/
H A Dcpu.c160 int fsl_qoriq_dsp_core_to_cluster(unsigned int core) in fsl_qoriq_dsp_core_to_cluster() argument
171 if (count == core) in fsl_qoriq_dsp_core_to_cluster()
183 int fsl_qoriq_core_to_cluster(unsigned int core) in fsl_qoriq_core_to_cluster() argument
194 if (count == core) in fsl_qoriq_core_to_cluster()
306 int is_core_valid(unsigned int core) in is_core_valid() argument
308 return !!((1 << core) & cpu_mask()); in is_core_valid()
/rk3399_rockchip-uboot/board/imgtec/malta/
H A Dmalta.c97 enum core_card core; in checkboard() local
102 core = malta_core_card(); in checkboard()
103 switch (core) { in checkboard()
/rk3399_rockchip-uboot/doc/
H A DREADME.VSC3316-330816 …point connections to be activated, 01.h value need to be written in 75.h (core configuration regis…
31 …e register, Global input ISE, Global input LOS, Global core control, Output mode register and core…
41 …For crosspoint connections to be activated, 01.h value need to be written in 75.h (core configurat…
H A DREADME.Heterogeneous-SoCs50 DSP/SC3900 core clusters
75 freq_processor_dsp[CONFIG_MAX_DSP_CPUS] - Array to contain the DSP core's frequencies
100 CPUn - PowerPC core
101 DSP CPUn - SC3900 core
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A DKconfig80 ARM core and more.
89 ARM core and more.
108 ARM core, a quad core PRU-ICSS for industrial Ethernet
124 ARM core, a dual core PRU-ICSS for industrial Ethernet
/rk3399_rockchip-uboot/board/freescale/p1022ds/
H A DREADME3 P1022ds is a Low End Dual core platform supporting the P1022 processor
4 of QorIQ series. P1022 is an e500 based dual core SOC.
/rk3399_rockchip-uboot/tools/patman/
H A Dsetup.py4 from distutils.core import setup
/rk3399_rockchip-uboot/drivers/mtd/nand/
H A DMakefile3 nandcore-objs := core.o bbt.o
/rk3399_rockchip-uboot/drivers/clk/uniphier/
H A DMakefile1 obj-y += clk-uniphier-core.o

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