1*552a848eSStefano Babic /*
2*552a848eSStefano Babic * (C) Copyright 2014
3*552a848eSStefano Babic * Gabriel Huau <contact@huau-gabriel.fr>
4*552a848eSStefano Babic *
5*552a848eSStefano Babic * (C) Copyright 2009 Freescale Semiconductor, Inc.
6*552a848eSStefano Babic *
7*552a848eSStefano Babic * SPDX-License-Identifier: GPL-2.0+
8*552a848eSStefano Babic */
9*552a848eSStefano Babic
10*552a848eSStefano Babic #include <common.h>
11*552a848eSStefano Babic #include <asm/io.h>
12*552a848eSStefano Babic #include <linux/errno.h>
13*552a848eSStefano Babic #include <asm/arch/sys_proto.h>
14*552a848eSStefano Babic #include <asm/arch/imx-regs.h>
15*552a848eSStefano Babic
16*552a848eSStefano Babic #define MAX_CPUS 4
17*552a848eSStefano Babic static struct src *src = (struct src *)SRC_BASE_ADDR;
18*552a848eSStefano Babic
19*552a848eSStefano Babic static uint32_t cpu_reset_mask[MAX_CPUS] = {
20*552a848eSStefano Babic 0, /* We don't really want to modify the cpu0 */
21*552a848eSStefano Babic SRC_SCR_CORE_1_RESET_MASK,
22*552a848eSStefano Babic SRC_SCR_CORE_2_RESET_MASK,
23*552a848eSStefano Babic SRC_SCR_CORE_3_RESET_MASK
24*552a848eSStefano Babic };
25*552a848eSStefano Babic
26*552a848eSStefano Babic static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
27*552a848eSStefano Babic 0, /* We don't really want to modify the cpu0 */
28*552a848eSStefano Babic SRC_SCR_CORE_1_ENABLE_MASK,
29*552a848eSStefano Babic SRC_SCR_CORE_2_ENABLE_MASK,
30*552a848eSStefano Babic SRC_SCR_CORE_3_ENABLE_MASK
31*552a848eSStefano Babic };
32*552a848eSStefano Babic
cpu_reset(int nr)33*552a848eSStefano Babic int cpu_reset(int nr)
34*552a848eSStefano Babic {
35*552a848eSStefano Babic /* Software reset of the CPU N */
36*552a848eSStefano Babic src->scr |= cpu_reset_mask[nr];
37*552a848eSStefano Babic return 0;
38*552a848eSStefano Babic }
39*552a848eSStefano Babic
cpu_status(int nr)40*552a848eSStefano Babic int cpu_status(int nr)
41*552a848eSStefano Babic {
42*552a848eSStefano Babic printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
43*552a848eSStefano Babic return 0;
44*552a848eSStefano Babic }
45*552a848eSStefano Babic
cpu_release(int nr,int argc,char * const argv[])46*552a848eSStefano Babic int cpu_release(int nr, int argc, char *const argv[])
47*552a848eSStefano Babic {
48*552a848eSStefano Babic uint32_t boot_addr;
49*552a848eSStefano Babic
50*552a848eSStefano Babic boot_addr = simple_strtoul(argv[0], NULL, 16);
51*552a848eSStefano Babic
52*552a848eSStefano Babic switch (nr) {
53*552a848eSStefano Babic case 1:
54*552a848eSStefano Babic src->gpr3 = boot_addr;
55*552a848eSStefano Babic break;
56*552a848eSStefano Babic case 2:
57*552a848eSStefano Babic src->gpr5 = boot_addr;
58*552a848eSStefano Babic break;
59*552a848eSStefano Babic case 3:
60*552a848eSStefano Babic src->gpr7 = boot_addr;
61*552a848eSStefano Babic break;
62*552a848eSStefano Babic default:
63*552a848eSStefano Babic return 1;
64*552a848eSStefano Babic }
65*552a848eSStefano Babic
66*552a848eSStefano Babic /* CPU N is ready to start */
67*552a848eSStefano Babic src->scr |= cpu_ctrl_mask[nr];
68*552a848eSStefano Babic
69*552a848eSStefano Babic return 0;
70*552a848eSStefano Babic }
71*552a848eSStefano Babic
is_core_valid(unsigned int core)72*552a848eSStefano Babic int is_core_valid(unsigned int core)
73*552a848eSStefano Babic {
74*552a848eSStefano Babic uint32_t nr_cores = get_nr_cpus();
75*552a848eSStefano Babic
76*552a848eSStefano Babic if (core > nr_cores)
77*552a848eSStefano Babic return 0;
78*552a848eSStefano Babic
79*552a848eSStefano Babic return 1;
80*552a848eSStefano Babic }
81*552a848eSStefano Babic
cpu_disable(int nr)82*552a848eSStefano Babic int cpu_disable(int nr)
83*552a848eSStefano Babic {
84*552a848eSStefano Babic /* Disable the CPU N */
85*552a848eSStefano Babic src->scr &= ~cpu_ctrl_mask[nr];
86*552a848eSStefano Babic return 0;
87*552a848eSStefano Babic }
88