1*09f455dcSMasahiro Yamada /*
2*09f455dcSMasahiro Yamada * Copyright (c) 2011 The Chromium OS Authors.
3*09f455dcSMasahiro Yamada * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
4*09f455dcSMasahiro Yamada *
5*09f455dcSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+
6*09f455dcSMasahiro Yamada */
7*09f455dcSMasahiro Yamada
8*09f455dcSMasahiro Yamada #include <common.h>
9*09f455dcSMasahiro Yamada #include <i2c.h>
10*09f455dcSMasahiro Yamada #include <tps6586x.h>
11*09f455dcSMasahiro Yamada #include <asm/io.h>
12*09f455dcSMasahiro Yamada #include <asm/arch/tegra.h>
13*09f455dcSMasahiro Yamada #include <asm/arch-tegra/ap.h>
14*09f455dcSMasahiro Yamada #include <asm/arch-tegra/tegra_i2c.h>
15*09f455dcSMasahiro Yamada #include <asm/arch-tegra/sys_proto.h>
16*09f455dcSMasahiro Yamada
17*09f455dcSMasahiro Yamada #define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */
18*09f455dcSMasahiro Yamada #define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */
19*09f455dcSMasahiro Yamada
20*09f455dcSMasahiro Yamada #define VDD_CORE_NOMINAL_T20 0x16 /* 1.275v */
21*09f455dcSMasahiro Yamada #define VDD_CPU_NOMINAL_T20 0x0f /* 1.1v */
22*09f455dcSMasahiro Yamada
23*09f455dcSMasahiro Yamada #define VDD_RELATION 0x02 /* 50mv */
24*09f455dcSMasahiro Yamada #define VDD_TRANSITION_STEP 0x06 /* 150mv */
25*09f455dcSMasahiro Yamada #define VDD_TRANSITION_RATE 0x06 /* 3.52mv/us */
26*09f455dcSMasahiro Yamada
27*09f455dcSMasahiro Yamada #define PMI_I2C_ADDRESS 0x34 /* chip requires this address */
28*09f455dcSMasahiro Yamada
pmu_set_nominal(void)29*09f455dcSMasahiro Yamada int pmu_set_nominal(void)
30*09f455dcSMasahiro Yamada {
31*09f455dcSMasahiro Yamada struct udevice *bus, *dev;
32*09f455dcSMasahiro Yamada int core, cpu;
33*09f455dcSMasahiro Yamada int ret;
34*09f455dcSMasahiro Yamada
35*09f455dcSMasahiro Yamada /* by default, the table has been filled with T25 settings */
36*09f455dcSMasahiro Yamada switch (tegra_get_chip_sku()) {
37*09f455dcSMasahiro Yamada case TEGRA_SOC_T20:
38*09f455dcSMasahiro Yamada core = VDD_CORE_NOMINAL_T20;
39*09f455dcSMasahiro Yamada cpu = VDD_CPU_NOMINAL_T20;
40*09f455dcSMasahiro Yamada break;
41*09f455dcSMasahiro Yamada case TEGRA_SOC_T25:
42*09f455dcSMasahiro Yamada core = VDD_CORE_NOMINAL_T25;
43*09f455dcSMasahiro Yamada cpu = VDD_CPU_NOMINAL_T25;
44*09f455dcSMasahiro Yamada break;
45*09f455dcSMasahiro Yamada default:
46*09f455dcSMasahiro Yamada debug("%s: Unknown SKU id\n", __func__);
47*09f455dcSMasahiro Yamada return -1;
48*09f455dcSMasahiro Yamada }
49*09f455dcSMasahiro Yamada
50*09f455dcSMasahiro Yamada ret = tegra_i2c_get_dvc_bus(&bus);
51*09f455dcSMasahiro Yamada if (ret) {
52*09f455dcSMasahiro Yamada debug("%s: Cannot find DVC I2C bus\n", __func__);
53*09f455dcSMasahiro Yamada return ret;
54*09f455dcSMasahiro Yamada }
55*09f455dcSMasahiro Yamada ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, 1, &dev);
56*09f455dcSMasahiro Yamada if (ret) {
57*09f455dcSMasahiro Yamada debug("%s: Cannot find DVC I2C chip\n", __func__);
58*09f455dcSMasahiro Yamada return ret;
59*09f455dcSMasahiro Yamada }
60*09f455dcSMasahiro Yamada
61*09f455dcSMasahiro Yamada tps6586x_init(dev);
62*09f455dcSMasahiro Yamada tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
63*09f455dcSMasahiro Yamada return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
64*09f455dcSMasahiro Yamada VDD_TRANSITION_RATE, VDD_RELATION);
65*09f455dcSMasahiro Yamada }
66