| /rk3399_rockchip-uboot/drivers/i2c/ |
| H A D | sh_sh7734_i2c.c | 159 clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY); in i2c_set_addr()
228 clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY); in i2c_raw_read()
234 clrsetbits_8(&base->iccr1, SH_I2C_ICCR1_TRS, SH_I2C_ICCR1_MST); in i2c_raw_read()
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| /rk3399_rockchip-uboot/board/freescale/corenet_ds/ |
| H A D | eth_hydra.c | 108 clrsetbits_8(&pixis->brdcfg1, mask, val); in hydra_mux_mdio()
500 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, in board_eth_init()
506 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, in board_eth_init()
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| H A D | eth_superhydra.c | 113 clrsetbits_8(&pixis->brdcfg1, mask, val); in super_hydra_mux_mdio()
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| /rk3399_rockchip-uboot/board/freescale/common/ |
| H A D | pixis.c | 113 clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll); in set_px_mpxpll()
149 clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val); in set_px_corepll()
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| /rk3399_rockchip-uboot/board/freescale/p1022ds/ |
| H A D | spl.c | 47 clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); in board_init_f()
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| H A D | p1022ds.c | 51 clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); in board_early_init_f()
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| /rk3399_rockchip-uboot/arch/x86/cpu/ivybridge/ |
| H A D | northbridge.c | 130 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); in northbridge_init()
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| H A D | lpc.c | 423 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod); in set_spi_speed()
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| /rk3399_rockchip-uboot/lib/ |
| H A D | uuid.c | 250 clrsetbits_8(&uuid->clock_seq_hi_and_reserved, in gen_rand_uuid()
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| /rk3399_rockchip-uboot/arch/m68k/cpu/mcf5445x/ |
| H A D | cpu_init.c | 415 clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK, in fecpin_setclear()
417 clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK, in fecpin_setclear()
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| /rk3399_rockchip-uboot/arch/sandbox/include/asm/ |
| H A D | io.h | 104 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | sh_qspi.c | 248 clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG, in spi_xfer()
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| H A D | bcm63xx_spi.c | 174 clrsetbits_8(priv->base + regs[SPI_CLK], in bcm63xx_spi_set_speed()
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| /rk3399_rockchip-uboot/arch/nios2/include/asm/ |
| H A D | io.h | 168 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /rk3399_rockchip-uboot/arch/arc/include/asm/ |
| H A D | io.h | 303 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /rk3399_rockchip-uboot/arch/x86/cpu/broadwell/ |
| H A D | pch.c | 445 clrsetbits_8(MCHBAR_REG(MCH_PAIR), 0x7, 0x4); /* Fixed Priority */ in systemagent_init()
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| /rk3399_rockchip-uboot/arch/x86/include/asm/ |
| H A D | io.h | 126 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /rk3399_rockchip-uboot/arch/sh/include/asm/ |
| H A D | io.h | 232 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /rk3399_rockchip-uboot/arch/m68k/include/asm/ |
| H A D | io.h | 246 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /rk3399_rockchip-uboot/arch/powerpc/include/asm/ |
| H A D | io.h | 283 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /rk3399_rockchip-uboot/arch/nds32/include/asm/ |
| H A D | io.h | 219 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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| /rk3399_rockchip-uboot/arch/arm/include/asm/ |
| H A D | io.h | 193 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) macro
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