| #
7f3cd1e4 |
| 10-Apr-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
UPSTREAM: spi: sh_qspi: Make use of the 32byte FIFO
The QSPI controller on RCar Gen2 has 32byte FIFO. Instead of doing the SPI transmission 1 byte at time, if there is a 32byte chunk of data to be t
UPSTREAM: spi: sh_qspi: Make use of the 32byte FIFO
The QSPI controller on RCar Gen2 has 32byte FIFO. Instead of doing the SPI transmission 1 byte at time, if there is a 32byte chunk of data to be transferred, fill the FIFO completely and then transfer the data to/from the FIFO. This increases the SPI NOR access speed significantly.
Change-Id: Idc0280488ce052492579ee8e52f6084aa0840f3b Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> (cherry picked from commit ea5512eb095067dda27930246792d2957feb9434)
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| #
9d14f4ef |
| 10-Apr-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
UPSTREAM: spi: sh_qspi: Replace ad hoc waiting with wait_for_bit
Replace the ad-hoc endless loops with wait_for_bit() with reasonable timeout. Note that the loops had internal 10uS delays, although
UPSTREAM: spi: sh_qspi: Replace ad hoc waiting with wait_for_bit
Replace the ad-hoc endless loops with wait_for_bit() with reasonable timeout. Note that the loops had internal 10uS delays, although there is no reason for those on this HW, so they are dropped.
Change-Id: I0d004adc09e2fb32e88b17b0f060aecc0b7bda35 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> (cherry picked from commit 9573db654d1999a1dfde6469782aa8d7cf3d589f)
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| #
2b8aed01 |
| 10-Apr-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
UPSTREAM: spi: sh_qspi: Drop SPBDCR wait
Waiting for SPBDCR == 1 is not required and is covered by the subsequent wait for SPSR_SPRFF, so drop this.
Change-Id: Ie943ac6feff57e478a7b2e7325eac9b5438c
UPSTREAM: spi: sh_qspi: Drop SPBDCR wait
Waiting for SPBDCR == 1 is not required and is covered by the subsequent wait for SPSR_SPRFF, so drop this.
Change-Id: Ie943ac6feff57e478a7b2e7325eac9b5438c0374 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> (cherry picked from commit 118226495249268a35e604b2e6309801699f6224)
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| #
7950bf5e |
| 10-Apr-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
UPSTREAM: spi: sh_qspi: Replace data types with short ones
Just replace unsigned {char,short,long} with u{8,16,32}, no functional change.
Change-Id: Ie9a9d331acb364d9b27a72a052a511a8da61c471 Signed
UPSTREAM: spi: sh_qspi: Replace data types with short ones
Just replace unsigned {char,short,long} with u{8,16,32}, no functional change.
Change-Id: Ie9a9d331acb364d9b27a72a052a511a8da61c471 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> (cherry picked from commit 0e6fa20b14ed27ef667ddb31c8e7c620417ee4f5)
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| #
24b852a7 |
| 09-Nov-2015 |
Simon Glass <sjg@chromium.org> |
Move console definitions into a new console.h file
The console includes a global variable and several functions that are only used by a small subset of U-Boot files. Before adding more functions, mo
Move console definitions into a new console.h file
The console includes a global variable and several functions that are only used by a small subset of U-Boot files. Before adding more functions, move the definitions into their own header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
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| #
e573bdb3 |
| 30-Oct-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
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| #
446d37c1 |
| 28-Oct-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-spi
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| #
ccaa9485 |
| 22-Oct-2015 |
Jagan Teki <jteki@openedev.com> |
spi: sh_qspi: Use BIT macro
Replace numerical bit shift with BIT macro in sh_qspi
:%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Review
spi: sh_qspi: Use BIT macro
Replace numerical bit shift with BIT macro in sh_qspi
:%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
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| #
707acd01 |
| 26-Jan-2014 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
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| #
4913fc23 |
| 16-Jan-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
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| #
22e75d6d |
| 08-Jan-2014 |
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
spi: sh_qspi: Add header file that defines the address of registers
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
spi: sh_qspi: Add header file that defines the address of registers
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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| #
1bbba03d |
| 19-Dec-2013 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-spi
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| #
16f47c9c |
| 18-Dec-2013 |
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
spi: Add support SH Quad SPI driver
This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash.
Signed-off-by: Kouei Abe <kouei.abe.cp@ren
spi: Add support SH Quad SPI driver
This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash.
Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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