xref: /rk3399_rockchip-uboot/arch/powerpc/include/asm/io.h (revision 5f5620ab2679608f94b3a77e51c77d0a770103bd)
1a47a12beSStefan Roese /* originally from linux source.
2a47a12beSStefan Roese  * removed the dependencies on CONFIG_ values
3a47a12beSStefan Roese  * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__)
4a47a12beSStefan Roese  * Modified By Rob Taylor, Flying Pig Systems, 2000
5a47a12beSStefan Roese  */
6a47a12beSStefan Roese 
7a47a12beSStefan Roese #ifndef _PPC_IO_H
8a47a12beSStefan Roese #define _PPC_IO_H
9a47a12beSStefan Roese 
10a47a12beSStefan Roese #include <asm/byteorder.h>
11a47a12beSStefan Roese 
12a47a12beSStefan Roese #ifdef CONFIG_ADDR_MAP
13a47a12beSStefan Roese #include <addr_map.h>
14a47a12beSStefan Roese #endif
15a47a12beSStefan Roese 
16a47a12beSStefan Roese #define SIO_CONFIG_RA   0x398
17a47a12beSStefan Roese #define SIO_CONFIG_RD   0x399
18a47a12beSStefan Roese 
19a47a12beSStefan Roese #ifndef _IO_BASE
20a47a12beSStefan Roese #define _IO_BASE 0
21a47a12beSStefan Roese #endif
22a47a12beSStefan Roese 
23a47a12beSStefan Roese #define readb(addr) in_8((volatile u8 *)(addr))
24a47a12beSStefan Roese #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
25a47a12beSStefan Roese #if !defined(__BIG_ENDIAN)
26a47a12beSStefan Roese #define readw(addr) (*(volatile u16 *) (addr))
27a47a12beSStefan Roese #define readl(addr) (*(volatile u32 *) (addr))
28a47a12beSStefan Roese #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
29a47a12beSStefan Roese #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
30a47a12beSStefan Roese #else
31a47a12beSStefan Roese #define readw(addr) in_le16((volatile u16 *)(addr))
32a47a12beSStefan Roese #define readl(addr) in_le32((volatile u32 *)(addr))
33a47a12beSStefan Roese #define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
34a47a12beSStefan Roese #define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
35a47a12beSStefan Roese #endif
36a47a12beSStefan Roese 
37a47a12beSStefan Roese /*
38a47a12beSStefan Roese  * The insw/outsw/insl/outsl macros don't do byte-swapping.
39a47a12beSStefan Roese  * They are only used in practice for transferring buffers which
40a47a12beSStefan Roese  * are arrays of bytes, and byte-swapping is not appropriate in
41a47a12beSStefan Roese  * that case.  - paulus
42a47a12beSStefan Roese  */
43a47a12beSStefan Roese #define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
44a47a12beSStefan Roese #define outsb(port, buf, ns)    _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
45a47a12beSStefan Roese #define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
46a47a12beSStefan Roese #define outsw(port, buf, ns)    _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
47a47a12beSStefan Roese #define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
48a47a12beSStefan Roese #define outsl(port, buf, nl)    _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
49a47a12beSStefan Roese 
50a47a12beSStefan Roese #define inb(port)       in_8((u8 *)((port)+_IO_BASE))
51a47a12beSStefan Roese #define outb(val, port)     out_8((u8 *)((port)+_IO_BASE), (val))
52a47a12beSStefan Roese #if !defined(__BIG_ENDIAN)
53a47a12beSStefan Roese #define inw(port)       in_be16((u16 *)((port)+_IO_BASE))
54a47a12beSStefan Roese #define outw(val, port)     out_be16((u16 *)((port)+_IO_BASE), (val))
55a47a12beSStefan Roese #define inl(port)       in_be32((u32 *)((port)+_IO_BASE))
56a47a12beSStefan Roese #define outl(val, port)     out_be32((u32 *)((port)+_IO_BASE), (val))
57a47a12beSStefan Roese #else
58a47a12beSStefan Roese #define inw(port)       in_le16((u16 *)((port)+_IO_BASE))
59a47a12beSStefan Roese #define outw(val, port)     out_le16((u16 *)((port)+_IO_BASE), (val))
60a47a12beSStefan Roese #define inl(port)       in_le32((u32 *)((port)+_IO_BASE))
61a47a12beSStefan Roese #define outl(val, port)     out_le32((u32 *)((port)+_IO_BASE), (val))
62a47a12beSStefan Roese #endif
63a47a12beSStefan Roese 
64a47a12beSStefan Roese #define inb_p(port)     in_8((u8 *)((port)+_IO_BASE))
65a47a12beSStefan Roese #define outb_p(val, port)   out_8((u8 *)((port)+_IO_BASE), (val))
66a47a12beSStefan Roese #define inw_p(port)     in_le16((u16 *)((port)+_IO_BASE))
67a47a12beSStefan Roese #define outw_p(val, port)   out_le16((u16 *)((port)+_IO_BASE), (val))
68a47a12beSStefan Roese #define inl_p(port)     in_le32((u32 *)((port)+_IO_BASE))
69a47a12beSStefan Roese #define outl_p(val, port)   out_le32((u32 *)((port)+_IO_BASE), (val))
70a47a12beSStefan Roese 
71a47a12beSStefan Roese extern void _insb(volatile u8 *port, void *buf, int ns);
72a47a12beSStefan Roese extern void _outsb(volatile u8 *port, const void *buf, int ns);
73a47a12beSStefan Roese extern void _insw(volatile u16 *port, void *buf, int ns);
74a47a12beSStefan Roese extern void _outsw(volatile u16 *port, const void *buf, int ns);
75a47a12beSStefan Roese extern void _insl(volatile u32 *port, void *buf, int nl);
76a47a12beSStefan Roese extern void _outsl(volatile u32 *port, const void *buf, int nl);
77a47a12beSStefan Roese extern void _insw_ns(volatile u16 *port, void *buf, int ns);
78a47a12beSStefan Roese extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
79a47a12beSStefan Roese extern void _insl_ns(volatile u32 *port, void *buf, int nl);
80a47a12beSStefan Roese extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
81a47a12beSStefan Roese 
82a47a12beSStefan Roese /*
83a47a12beSStefan Roese  * The *_ns versions below don't do byte-swapping.
84a47a12beSStefan Roese  * Neither do the standard versions now, these are just here
85a47a12beSStefan Roese  * for older code.
86a47a12beSStefan Roese  */
87a47a12beSStefan Roese #define insw_ns(port, buf, ns)  _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
88a47a12beSStefan Roese #define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
89a47a12beSStefan Roese #define insl_ns(port, buf, nl)  _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
90a47a12beSStefan Roese #define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
91a47a12beSStefan Roese 
92a47a12beSStefan Roese 
93a47a12beSStefan Roese #define IO_SPACE_LIMIT ~0
94a47a12beSStefan Roese 
95a47a12beSStefan Roese #define memset_io(a,b,c)       memset((void *)(a),(b),(c))
96a47a12beSStefan Roese #define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
97a47a12beSStefan Roese #define memcpy_toio(a,b,c)  memcpy((void *)(a),(b),(c))
98a47a12beSStefan Roese 
99a47a12beSStefan Roese /*
100a47a12beSStefan Roese  * Enforce In-order Execution of I/O:
101a47a12beSStefan Roese  * Acts as a barrier to ensure all previous I/O accesses have
102a47a12beSStefan Roese  * completed before any further ones are issued.
103a47a12beSStefan Roese  */
eieio(void)104a47a12beSStefan Roese static inline void eieio(void)
105a47a12beSStefan Roese {
106a47a12beSStefan Roese 	__asm__ __volatile__ ("eieio" : : : "memory");
107a47a12beSStefan Roese }
108a47a12beSStefan Roese 
sync(void)109a47a12beSStefan Roese static inline void sync(void)
110a47a12beSStefan Roese {
111a47a12beSStefan Roese 	__asm__ __volatile__ ("sync" : : : "memory");
112a47a12beSStefan Roese }
113a47a12beSStefan Roese 
isync(void)114a47a12beSStefan Roese static inline void isync(void)
115a47a12beSStefan Roese {
116a47a12beSStefan Roese 	__asm__ __volatile__ ("isync" : : : "memory");
117a47a12beSStefan Roese }
118a47a12beSStefan Roese 
119a47a12beSStefan Roese /* Enforce in-order execution of data I/O.
120a47a12beSStefan Roese  * No distinction between read/write on PPC; use eieio for all three.
121a47a12beSStefan Roese  */
122a47a12beSStefan Roese #define iobarrier_rw() eieio()
123a47a12beSStefan Roese #define iobarrier_r()  eieio()
124a47a12beSStefan Roese #define iobarrier_w()  eieio()
125a47a12beSStefan Roese 
1268340e7acSYork Sun #define mb()	sync()
1278340e7acSYork Sun #define isb()	isync()
1288340e7acSYork Sun 
129a47a12beSStefan Roese /*
130a47a12beSStefan Roese  * Non ordered and non-swapping "raw" accessors
131a47a12beSStefan Roese  */
132a47a12beSStefan Roese #define PCI_FIX_ADDR(addr)	(addr)
133a47a12beSStefan Roese 
__raw_readb(const volatile void __iomem * addr)134a47a12beSStefan Roese static inline unsigned char __raw_readb(const volatile void __iomem *addr)
135a47a12beSStefan Roese {
136a47a12beSStefan Roese 	return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
137a47a12beSStefan Roese }
__raw_readw(const volatile void __iomem * addr)138a47a12beSStefan Roese static inline unsigned short __raw_readw(const volatile void __iomem *addr)
139a47a12beSStefan Roese {
140a47a12beSStefan Roese 	return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
141a47a12beSStefan Roese }
__raw_readl(const volatile void __iomem * addr)142a47a12beSStefan Roese static inline unsigned int __raw_readl(const volatile void __iomem *addr)
143a47a12beSStefan Roese {
144a47a12beSStefan Roese 	return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
145a47a12beSStefan Roese }
__raw_writeb(unsigned char v,volatile void __iomem * addr)146a47a12beSStefan Roese static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
147a47a12beSStefan Roese {
148a47a12beSStefan Roese 	*(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
149a47a12beSStefan Roese }
__raw_writew(unsigned short v,volatile void __iomem * addr)150a47a12beSStefan Roese static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
151a47a12beSStefan Roese {
152a47a12beSStefan Roese 	*(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
153a47a12beSStefan Roese }
__raw_writel(unsigned int v,volatile void __iomem * addr)154a47a12beSStefan Roese static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
155a47a12beSStefan Roese {
156a47a12beSStefan Roese 	*(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
157a47a12beSStefan Roese }
158a47a12beSStefan Roese 
159a47a12beSStefan Roese /*
160a47a12beSStefan Roese  * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
161a47a12beSStefan Roese  *
162a47a12beSStefan Roese  * Read operations have additional twi & isync to make sure the read
163a47a12beSStefan Roese  * is actually performed (i.e. the data has come back) before we start
164a47a12beSStefan Roese  * executing any following instructions.
165a47a12beSStefan Roese  */
in_8(const volatile unsigned char __iomem * addr)166*44d0677aSMåns Rullgård static inline u8 in_8(const volatile unsigned char __iomem *addr)
167a47a12beSStefan Roese {
168a16a5cccSPrabhakar Kushwaha 	u8 ret;
169a47a12beSStefan Roese 
170a47a12beSStefan Roese 	__asm__ __volatile__(
171a47a12beSStefan Roese 		"sync; lbz%U1%X1 %0,%1;\n"
172a47a12beSStefan Roese 		"twi 0,%0,0;\n"
173a47a12beSStefan Roese 		"isync" : "=r" (ret) : "m" (*addr));
174a47a12beSStefan Roese 	return ret;
175a47a12beSStefan Roese }
176a47a12beSStefan Roese 
out_8(volatile unsigned char __iomem * addr,u8 val)177*44d0677aSMåns Rullgård static inline void out_8(volatile unsigned char __iomem *addr, u8 val)
178a47a12beSStefan Roese {
1791fade702STimur Tabi 	__asm__ __volatile__("sync;\n"
1801fade702STimur Tabi 			     "stb%U0%X0 %1,%0;\n"
1811fade702STimur Tabi 			     : "=m" (*addr)
1821fade702STimur Tabi 			     : "r" (val));
183a47a12beSStefan Roese }
184a47a12beSStefan Roese 
in_le16(const volatile unsigned short __iomem * addr)185*44d0677aSMåns Rullgård static inline u16 in_le16(const volatile unsigned short __iomem *addr)
186a47a12beSStefan Roese {
187a16a5cccSPrabhakar Kushwaha 	u16 ret;
188a47a12beSStefan Roese 
189a47a12beSStefan Roese 	__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
190a47a12beSStefan Roese 			     "twi 0,%0,0;\n"
191a47a12beSStefan Roese 			     "isync" : "=r" (ret) :
192a47a12beSStefan Roese 			      "r" (addr), "m" (*addr));
193a47a12beSStefan Roese 	return ret;
194a47a12beSStefan Roese }
195a47a12beSStefan Roese 
in_be16(const volatile unsigned short __iomem * addr)196*44d0677aSMåns Rullgård static inline u16 in_be16(const volatile unsigned short __iomem *addr)
197a47a12beSStefan Roese {
198a16a5cccSPrabhakar Kushwaha 	u16 ret;
199a47a12beSStefan Roese 
200a47a12beSStefan Roese 	__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
201a47a12beSStefan Roese 			     "twi 0,%0,0;\n"
202a47a12beSStefan Roese 			     "isync" : "=r" (ret) : "m" (*addr));
203a47a12beSStefan Roese 	return ret;
204a47a12beSStefan Roese }
205a47a12beSStefan Roese 
out_le16(volatile unsigned short __iomem * addr,u16 val)206*44d0677aSMåns Rullgård static inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
207a47a12beSStefan Roese {
208a47a12beSStefan Roese 	__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
209a47a12beSStefan Roese 			      "r" (val), "r" (addr));
210a47a12beSStefan Roese }
211a47a12beSStefan Roese 
out_be16(volatile unsigned short __iomem * addr,u16 val)212*44d0677aSMåns Rullgård static inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
213a47a12beSStefan Roese {
214a47a12beSStefan Roese 	__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
215a47a12beSStefan Roese }
216a47a12beSStefan Roese 
in_le32(const volatile unsigned __iomem * addr)217*44d0677aSMåns Rullgård static inline u32 in_le32(const volatile unsigned __iomem *addr)
218a47a12beSStefan Roese {
219a16a5cccSPrabhakar Kushwaha 	u32 ret;
220a47a12beSStefan Roese 
221a47a12beSStefan Roese 	__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
222a47a12beSStefan Roese 			     "twi 0,%0,0;\n"
223a47a12beSStefan Roese 			     "isync" : "=r" (ret) :
224a47a12beSStefan Roese 			     "r" (addr), "m" (*addr));
225a47a12beSStefan Roese 	return ret;
226a47a12beSStefan Roese }
227a47a12beSStefan Roese 
in_be32(const volatile unsigned __iomem * addr)228*44d0677aSMåns Rullgård static inline u32 in_be32(const volatile unsigned __iomem *addr)
229a47a12beSStefan Roese {
230a16a5cccSPrabhakar Kushwaha 	u32 ret;
231a47a12beSStefan Roese 
232a47a12beSStefan Roese 	__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
233a47a12beSStefan Roese 			     "twi 0,%0,0;\n"
234a47a12beSStefan Roese 			     "isync" : "=r" (ret) : "m" (*addr));
235a47a12beSStefan Roese 	return ret;
236a47a12beSStefan Roese }
237a47a12beSStefan Roese 
out_le32(volatile unsigned __iomem * addr,u32 val)238*44d0677aSMåns Rullgård static inline void out_le32(volatile unsigned __iomem *addr, u32 val)
239a47a12beSStefan Roese {
240a47a12beSStefan Roese 	__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
241a47a12beSStefan Roese 			     "r" (val), "r" (addr));
242a47a12beSStefan Roese }
243a47a12beSStefan Roese 
out_be32(volatile unsigned __iomem * addr,u32 val)244*44d0677aSMåns Rullgård static inline void out_be32(volatile unsigned __iomem *addr, u32 val)
245a47a12beSStefan Roese {
246a47a12beSStefan Roese 	__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
247a47a12beSStefan Roese }
248a47a12beSStefan Roese 
249a47a12beSStefan Roese /* Clear and set bits in one shot. These macros can be used to clear and
250a47a12beSStefan Roese  * set multiple bits in a register using a single call. These macros can
251a47a12beSStefan Roese  * also be used to set a multiple-bit bit pattern using a mask, by
252a47a12beSStefan Roese  * specifying the mask in the 'clear' parameter and the new bit pattern
253a47a12beSStefan Roese  * in the 'set' parameter.
254a47a12beSStefan Roese  */
255a47a12beSStefan Roese 
256a47a12beSStefan Roese #define clrbits(type, addr, clear) \
257a47a12beSStefan Roese 	out_##type((addr), in_##type(addr) & ~(clear))
258a47a12beSStefan Roese 
259a47a12beSStefan Roese #define setbits(type, addr, set) \
260a47a12beSStefan Roese 	out_##type((addr), in_##type(addr) | (set))
261a47a12beSStefan Roese 
262a47a12beSStefan Roese #define clrsetbits(type, addr, clear, set) \
263a47a12beSStefan Roese 	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
264a47a12beSStefan Roese 
265a47a12beSStefan Roese #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
266a47a12beSStefan Roese #define setbits_be32(addr, set) setbits(be32, addr, set)
267a47a12beSStefan Roese #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
268a47a12beSStefan Roese 
269a47a12beSStefan Roese #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
270a47a12beSStefan Roese #define setbits_le32(addr, set) setbits(le32, addr, set)
271a47a12beSStefan Roese #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
272a47a12beSStefan Roese 
273a47a12beSStefan Roese #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
274a47a12beSStefan Roese #define setbits_be16(addr, set) setbits(be16, addr, set)
275a47a12beSStefan Roese #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
276a47a12beSStefan Roese 
277a47a12beSStefan Roese #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
278a47a12beSStefan Roese #define setbits_le16(addr, set) setbits(le16, addr, set)
279a47a12beSStefan Roese #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
280a47a12beSStefan Roese 
281a47a12beSStefan Roese #define clrbits_8(addr, clear) clrbits(8, addr, clear)
282a47a12beSStefan Roese #define setbits_8(addr, set) setbits(8, addr, set)
283a47a12beSStefan Roese #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
284a47a12beSStefan Roese 
285a47a12beSStefan Roese /*
286a47a12beSStefan Roese  * Given a physical address and a length, return a virtual address
287a47a12beSStefan Roese  * that can be used to access the memory range with the caching
288a47a12beSStefan Roese  * properties specified by "flags".
289a47a12beSStefan Roese  */
290a47a12beSStefan Roese #define MAP_NOCACHE	(0)
291a47a12beSStefan Roese #define MAP_WRCOMBINE	(0)
292a47a12beSStefan Roese #define MAP_WRBACK	(0)
293a47a12beSStefan Roese #define MAP_WRTHROUGH	(0)
294a47a12beSStefan Roese 
295a47a12beSStefan Roese static inline void *
map_physmem(phys_addr_t paddr,unsigned long len,unsigned long flags)296a47a12beSStefan Roese map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
297a47a12beSStefan Roese {
298a47a12beSStefan Roese #ifdef CONFIG_ADDR_MAP
2997b6e8053STimur Tabi 	return addrmap_phys_to_virt(paddr);
300a47a12beSStefan Roese #else
301a47a12beSStefan Roese 	return (void *)((unsigned long)paddr);
302a47a12beSStefan Roese #endif
303a47a12beSStefan Roese }
304a47a12beSStefan Roese 
305a47a12beSStefan Roese /*
306a47a12beSStefan Roese  * Take down a mapping set up by map_physmem().
307a47a12beSStefan Roese  */
unmap_physmem(void * vaddr,unsigned long flags)308a47a12beSStefan Roese static inline void unmap_physmem(void *vaddr, unsigned long flags)
309a47a12beSStefan Roese {
310a47a12beSStefan Roese 
311a47a12beSStefan Roese }
312a47a12beSStefan Roese 
virt_to_phys(void * vaddr)313a47a12beSStefan Roese static inline phys_addr_t virt_to_phys(void * vaddr)
314a47a12beSStefan Roese {
315a47a12beSStefan Roese #ifdef CONFIG_ADDR_MAP
316a47a12beSStefan Roese 	return addrmap_virt_to_phys(vaddr);
317a47a12beSStefan Roese #else
318a47a12beSStefan Roese 	return (phys_addr_t)((unsigned long)vaddr);
319a47a12beSStefan Roese #endif
320a47a12beSStefan Roese }
321a47a12beSStefan Roese 
322a47a12beSStefan Roese #endif
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