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Searched refs:clk (Results 1 – 25 of 533) sorted by relevance

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/rk3399_rockchip-uboot/drivers/clk/tegra/
H A Dtegra-car-clk.c13 static int tegra_car_clk_request(struct clk *clk) in tegra_car_clk_request() argument
15 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra_car_clk_request()
16 clk->id); in tegra_car_clk_request()
26 if (clk->id >= PERIPH_ID_COUNT) in tegra_car_clk_request()
32 static int tegra_car_clk_free(struct clk *clk) in tegra_car_clk_free() argument
34 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra_car_clk_free()
35 clk->id); in tegra_car_clk_free()
40 static ulong tegra_car_clk_get_rate(struct clk *clk) in tegra_car_clk_get_rate() argument
44 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra_car_clk_get_rate()
45 clk->id); in tegra_car_clk_get_rate()
[all …]
H A Dtegra186-clk.c13 static ulong tegra186_clk_get_rate(struct clk *clk) in tegra186_clk_get_rate() argument
19 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra186_clk_get_rate()
20 clk->id); in tegra186_clk_get_rate()
22 req.cmd_and_id = (CMD_CLK_GET_RATE << 24) | clk->id; in tegra186_clk_get_rate()
24 ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp, in tegra186_clk_get_rate()
32 static ulong tegra186_clk_set_rate(struct clk *clk, ulong rate) in tegra186_clk_set_rate() argument
38 debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate, in tegra186_clk_set_rate()
39 clk->dev, clk->id); in tegra186_clk_set_rate()
41 req.cmd_and_id = (CMD_CLK_SET_RATE << 24) | clk->id; in tegra186_clk_set_rate()
44 ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp, in tegra186_clk_set_rate()
[all …]
/rk3399_rockchip-uboot/include/
H A Dclk.h54 struct clk { struct
76 struct clk *clks; argument
83 struct phandle_1_arg *cells, struct clk *clk);
100 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
132 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk);
146 int clk_release_all(struct clk *clk, int count);
150 struct clk *clk) in clk_get_by_index() argument
161 struct clk *clk) in clk_get_by_name() argument
166 static inline int clk_release_all(struct clk *clk, int count) in clk_release_all() argument
219 int clk_request(struct udevice *dev, struct clk *clk);
[all …]
H A Dclk-uclass.h40 int (*of_xlate)(struct clk *clock,
55 int (*request)(struct clk *clock);
64 int (*free)(struct clk *clock);
71 ulong (*get_rate)(struct clk *clk);
79 ulong (*set_rate)(struct clk *clk, ulong rate);
87 int (*get_phase)(struct clk *clk);
96 int (*set_phase)(struct clk *clk, int degrees);
104 int (*set_parent)(struct clk *clk, struct clk *parent);
111 int (*enable)(struct clk *clk);
118 int (*disable)(struct clk *clk);
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dclock_init_exynos4.c41 struct exynos4_clock *clk = in system_clock_init() local
44 writel(CLK_SRC_CPU_VAL, &clk->src_cpu); in system_clock_init()
48 writel(CLK_SRC_TOP0_VAL, &clk->src_top0); in system_clock_init()
49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
50 writel(CLK_SRC_DMC_VAL, &clk->src_dmc); in system_clock_init()
51 writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus); in system_clock_init()
52 writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus); in system_clock_init()
53 writel(CLK_SRC_FSYS_VAL, &clk->src_fsys); in system_clock_init()
54 writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0); in system_clock_init()
55 writel(CLK_SRC_CAM_VAL, &clk->src_cam); in system_clock_init()
[all …]
H A Dclock_init_exynos5.c552 struct exynos5_clock *clk = in exynos5250_system_clock_init() local
561 clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); in exynos5250_system_clock_init()
563 val = readl(&clk->mux_stat_cpu); in exynos5250_system_clock_init()
566 clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK); in exynos5250_system_clock_init()
568 val = readl(&clk->mux_stat_core1); in exynos5250_system_clock_init()
571 clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); in exynos5250_system_clock_init()
572 clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); in exynos5250_system_clock_init()
573 clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); in exynos5250_system_clock_init()
574 clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); in exynos5250_system_clock_init()
578 val = readl(&clk->mux_stat_top2); in exynos5250_system_clock_init()
[all …]
H A Dclock.c188 struct exynos4_clock *clk = in exynos4_get_pll_clk() local
194 r = readl(&clk->apll_con0); in exynos4_get_pll_clk()
197 r = readl(&clk->mpll_con0); in exynos4_get_pll_clk()
200 r = readl(&clk->epll_con0); in exynos4_get_pll_clk()
201 k = readl(&clk->epll_con1); in exynos4_get_pll_clk()
204 r = readl(&clk->vpll_con0); in exynos4_get_pll_clk()
205 k = readl(&clk->vpll_con1); in exynos4_get_pll_clk()
218 struct exynos4x12_clock *clk = in exynos4x12_get_pll_clk() local
224 r = readl(&clk->apll_con0); in exynos4x12_get_pll_clk()
227 r = readl(&clk->mpll_con0); in exynos4x12_get_pll_clk()
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dstih410-clock.dtsi15 compatible = "st,stih410-clk", "simple-bus";
20 clk_sysin: clk-sysin {
30 arm_periph_clk: clk-m-a9-periphs {
58 clk_m_a9: clk-m-a9@92b0000 {
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
78 clock-output-names = "clk-m-a9-ext2f-div2";
92 clock-output-names = "clk-s-icn-reg-0";
99 clk_s_a0_pll: clk-s-a0-pll {
105 clock-output-names = "clk-s-a0-pll-ofd-0";
106 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
[all …]
H A Dstih407-clock.dtsi18 clk_sysin: clk-sysin {
27 arm_periph_clk: clk-m-a9-periphs {
56 clk_m_a9: clk-m-a9@92b0000 {
70 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
76 clock-output-names = "clk-m-a9-ext2f-div2";
90 clock-output-names = "clk-s-icn-reg-0";
97 clk_s_a0_pll: clk-s-a0-pll {
103 clock-output-names = "clk-s-a0-pll-ofd-0";
106 clk_s_a0_flexgen: clk-s-a0-flexgen {
114 clock-output-names = "clk-ic-lmi0";
[all …]
/rk3399_rockchip-uboot/drivers/clk/
H A Dclk-uclass.c27 struct phandle_1_arg *cells, struct clk *clk) in clk_get_by_index_platdata() argument
33 ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev); in clk_get_by_index_platdata()
36 clk->id = cells[0].arg[0]; in clk_get_by_index_platdata()
41 static int clk_of_xlate_default(struct clk *clk, in clk_of_xlate_default() argument
44 debug("%s(clk=%p)\n", __func__, clk); in clk_of_xlate_default()
52 clk->id = args->args[0]; in clk_of_xlate_default()
54 clk->id = 0; in clk_of_xlate_default()
60 int index, struct clk *clk) in clk_get_by_indexed_prop() argument
67 debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk); in clk_get_by_indexed_prop()
69 assert(clk); in clk_get_by_indexed_prop()
[all …]
H A Dclk_sandbox.c18 static ulong sandbox_clk_get_rate(struct clk *clk) in sandbox_clk_get_rate() argument
20 struct sandbox_clk_priv *priv = dev_get_priv(clk->dev); in sandbox_clk_get_rate()
22 if (clk->id >= SANDBOX_CLK_ID_COUNT) in sandbox_clk_get_rate()
25 return priv->rate[clk->id]; in sandbox_clk_get_rate()
28 static ulong sandbox_clk_set_rate(struct clk *clk, ulong rate) in sandbox_clk_set_rate() argument
30 struct sandbox_clk_priv *priv = dev_get_priv(clk->dev); in sandbox_clk_set_rate()
33 if (clk->id >= SANDBOX_CLK_ID_COUNT) in sandbox_clk_set_rate()
39 old_rate = priv->rate[clk->id]; in sandbox_clk_set_rate()
40 priv->rate[clk->id] = rate; in sandbox_clk_set_rate()
45 static int sandbox_clk_enable(struct clk *clk) in sandbox_clk_enable() argument
[all …]
H A Dclk_scmi.c12 static int scmi_clk_gate(struct clk *clk, int enable) in scmi_clk_gate() argument
15 .clock_id = clk->id, in scmi_clk_gate()
24 ret = devm_scmi_process_msg(clk->dev->parent, &msg); in scmi_clk_gate()
31 static int scmi_clk_enable(struct clk *clk) in scmi_clk_enable() argument
33 return scmi_clk_gate(clk, 1); in scmi_clk_enable()
36 static int scmi_clk_disable(struct clk *clk) in scmi_clk_disable() argument
38 return scmi_clk_gate(clk, 0); in scmi_clk_disable()
41 static ulong scmi_clk_get_rate(struct clk *clk) in scmi_clk_get_rate() argument
44 .clock_id = clk->id, in scmi_clk_get_rate()
52 ret = devm_scmi_process_msg(clk->dev->parent, &msg); in scmi_clk_get_rate()
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/kona-common/
H A Dclk.h14 struct clk;
18 struct clk *clk_get(const char *id);
19 int clk_enable(struct clk *clk);
20 void clk_disable(struct clk *clk);
21 unsigned long clk_get_rate(struct clk *clk);
22 long clk_round_rate(struct clk *clk, unsigned long rate);
23 int clk_set_rate(struct clk *clk, unsigned long rate);
24 int clk_set_parent(struct clk *clk, struct clk *parent);
25 struct clk *clk_get_parent(struct clk *clk);
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/clk/
H A DMakefile7 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
9 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
10 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
11 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
12 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
16 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
17 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
18 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o
19 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
[all …]
/rk3399_rockchip-uboot/board/samsung/trats/
H A Dtrats.c58 struct exynos4_clock *clk = in trats_low_power_mode() local
72 writel(0xa0c80604, &clk->apll_con0); in trats_low_power_mode()
79 writel(0x00000100, &clk->div_cpu0); in trats_low_power_mode()
82 while (readl(&clk->div_stat_cpu0) & 0x1111111) in trats_low_power_mode()
90 writel(0x13113117, &clk->div_dmc0); in trats_low_power_mode()
93 while (readl(&clk->div_stat_dmc0) & 0x11111111) in trats_low_power_mode()
106 writel(0x0, &clk->gate_ip_cam); /* CAM */ in trats_low_power_mode()
107 writel(0x0, &clk->gate_ip_tv); /* TV */ in trats_low_power_mode()
108 writel(0x0, &clk->gate_ip_mfc); /* MFC */ in trats_low_power_mode()
109 writel(0x0, &clk->gate_ip_g3d); /* G3D */ in trats_low_power_mode()
[all …]
/rk3399_rockchip-uboot/drivers/mtd/nand/raw/brcmnand/
H A Dbrcmnand_compat.c6 struct clk *devm_clk_get(struct udevice *dev, const char *id) in devm_clk_get()
8 struct clk *clk; in devm_clk_get() local
11 clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); in devm_clk_get()
12 if (!clk) { in devm_clk_get()
17 ret = clk_get_by_name(dev, id, clk); in devm_clk_get()
23 return clk; in devm_clk_get()
26 int clk_prepare_enable(struct clk *clk) in clk_prepare_enable() argument
28 return clk_enable(clk); in clk_prepare_enable()
31 void clk_disable_unprepare(struct clk *clk) in clk_disable_unprepare() argument
33 clk_disable(clk); in clk_disable_unprepare()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-bcm235xx.c26 .clk = { \
44 DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
45 DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
46 DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
48 DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
49 DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2);
50 DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4);
271 .clk = {
290 .clk = {
310 .clk = {
[all …]
H A Dclk-core.h26 struct clk;
31 struct clk *clk; member
51 int (*enable)(struct clk *c, int enable);
52 int (*set_rate)(struct clk *c, unsigned long rate);
53 unsigned long (*get_rate)(struct clk *c);
54 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
55 int (*set_parent)(struct clk *c, struct clk *parent);
58 struct clk { struct
59 struct clk *parent; argument
411 struct clk clk; member
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-bcm281xx.c26 .clk = { \
44 DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
45 DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
46 DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
48 DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
49 DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2);
50 DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4);
271 .clk = {
290 .clk = {
314 .clk = {
[all …]
H A Dclk-core.h26 struct clk;
31 struct clk *clk; member
51 int (*enable) (struct clk *c, int enable);
52 int (*set_rate) (struct clk *c, unsigned long rate);
53 unsigned long (*get_rate) (struct clk *c);
54 unsigned long (*round_rate) (struct clk *c, unsigned long rate);
55 int (*set_parent) (struct clk *c, struct clk *parent);
58 struct clk { struct
59 struct clk *parent; argument
411 struct clk clk; member
[all …]
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3308.c196 static ulong rk3308_i2c_get_clk(struct clk *clk) in rk3308_i2c_get_clk() argument
198 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_i2c_get_clk()
202 switch (clk->id) { in rk3308_i2c_get_clk()
226 static ulong rk3308_i2c_set_clk(struct clk *clk, uint hz) in rk3308_i2c_set_clk() argument
228 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_i2c_set_clk()
235 switch (clk->id) { in rk3308_i2c_set_clk()
257 return rk3308_i2c_get_clk(clk); in rk3308_i2c_set_clk()
260 static ulong rk3308_mac_set_clk(struct clk *clk, uint hz) in rk3308_mac_set_clk() argument
262 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_mac_set_clk()
290 static int rk3308_mac_set_speed_clk(struct clk *clk, uint hz) in rk3308_mac_set_speed_clk() argument
[all …]
/rk3399_rockchip-uboot/drivers/video/
H A Dipu.h23 struct clk { struct
27 struct clk *parent; argument
29 struct clk *secondary; argument
43 void (*recalc) (struct clk *); argument
49 int (*set_rate) (struct clk *, unsigned long); argument
54 unsigned long (*round_rate) (struct clk *, unsigned long); argument
59 int (*enable) (struct clk *); argument
64 void (*disable) (struct clk *); argument
66 int (*set_parent) (struct clk *, struct clk *); argument
245 void clk_enable(struct clk *clk);
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx7ulp/
H A Dpcc.c84 int pcc_clock_enable(enum pcc_clk clk, bool enable) in pcc_clock_enable() argument
88 if (clk >= ARRAY_SIZE(pcc_arrays)) in pcc_clock_enable()
91 reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; in pcc_clock_enable()
96 clk, reg, val, enable); in pcc_clock_enable()
114 int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src) in pcc_clock_sel() argument
118 if (clk >= ARRAY_SIZE(pcc_arrays)) in pcc_clock_sel()
121 clksrc_type = pcc_arrays[clk].clksrc; in pcc_clock_sel()
124 clk, clksrc_type); in pcc_clock_sel()
136 printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src); in pcc_clock_sel()
140 reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; in pcc_clock_sel()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/
H A Dclock.c28 struct s5pc100_clock *clk = in s5pc100_get_pll_clk() local
35 r = readl(&clk->apll_con); in s5pc100_get_pll_clk()
38 r = readl(&clk->mpll_con); in s5pc100_get_pll_clk()
41 r = readl(&clk->epll_con); in s5pc100_get_pll_clk()
44 r = readl(&clk->hpll_con); in s5pc100_get_pll_clk()
79 struct s5pc110_clock *clk = in s5pc110_get_pll_clk() local
86 r = readl(&clk->apll_con); in s5pc110_get_pll_clk()
89 r = readl(&clk->mpll_con); in s5pc110_get_pll_clk()
92 r = readl(&clk->epll_con); in s5pc110_get_pll_clk()
95 r = readl(&clk->vpll_con); in s5pc110_get_pll_clk()
[all …]
/rk3399_rockchip-uboot/drivers/clk/at91/
H A DMakefile6 obj-y += clk-slow.o clk-main.o clk-plla.o clk-master.o
7 obj-y += clk-system.o clk-peripheral.o
9 obj-$(CONFIG_AT91_UTMI) += clk-utmi.o
10 obj-$(CONFIG_AT91_H32MX) += clk-h32mx.o
11 obj-$(CONFIG_AT91_GENERIC_CLK) += clk-generated.o

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