58 	struct exynos4_clock *clk =  in trats_low_power_mode()  local
72 	writel(0xa0c80604, &clk->apll_con0);  in trats_low_power_mode()
79 	writel(0x00000100, &clk->div_cpu0);  in trats_low_power_mode()
82 	while (readl(&clk->div_stat_cpu0) & 0x1111111)  in trats_low_power_mode()
90 	writel(0x13113117, &clk->div_dmc0);  in trats_low_power_mode()
93 	while (readl(&clk->div_stat_dmc0) & 0x11111111)  in trats_low_power_mode()
106 	writel(0x0, &clk->gate_ip_cam);	/* CAM */  in trats_low_power_mode()
107 	writel(0x0, &clk->gate_ip_tv);          /* TV */  in trats_low_power_mode()
108 	writel(0x0, &clk->gate_ip_mfc);	/* MFC */  in trats_low_power_mode()
109 	writel(0x0, &clk->gate_ip_g3d);	/* G3D */  in trats_low_power_mode()
110 	writel(0x0, &clk->gate_ip_image);	/* IMAGE */  in trats_low_power_mode()
111 	writel(0x0, &clk->gate_ip_gps);	/* GPS */  in trats_low_power_mode()
317 	struct exynos4_clock *clk =  in board_clock_init()  local
320 	writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);  in board_clock_init()
321 	writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);  in board_clock_init()
322 	writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);  in board_clock_init()
323 	writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);  in board_clock_init()
325 	writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);  in board_clock_init()
326 	writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);  in board_clock_init()
327 	writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);  in board_clock_init()
328 	writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);  in board_clock_init()
329 	writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);  in board_clock_init()
330 	writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);  in board_clock_init()
331 	writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);  in board_clock_init()
332 	writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);  in board_clock_init()
333 	writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);  in board_clock_init()
334 	writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);  in board_clock_init()
335 	writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);  in board_clock_init()
336 	writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);  in board_clock_init()
338 	writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);  in board_clock_init()
339 	writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);  in board_clock_init()
340 	writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);  in board_clock_init()
341 	writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);  in board_clock_init()
342 	writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);  in board_clock_init()
343 	writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);  in board_clock_init()
344 	writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);  in board_clock_init()
345 	writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);  in board_clock_init()
346 	writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);  in board_clock_init()
347 	writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);  in board_clock_init()
348 	writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);  in board_clock_init()
349 	writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);  in board_clock_init()
351 	writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);  in board_clock_init()
352 	writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);  in board_clock_init()
353 	writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);  in board_clock_init()
354 	writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);  in board_clock_init()
355 	writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);  in board_clock_init()
356 	writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);  in board_clock_init()
357 	writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);  in board_clock_init()
358 	writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);  in board_clock_init()
359 	writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);  in board_clock_init()
360 	writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);  in board_clock_init()
361 	writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);  in board_clock_init()
362 	writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);  in board_clock_init()