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/rk3399_rockchip-uboot/arch/x86/lib/
H A Dmrccache.c22 struct mrc_data_container *cache) in next_mrc_block() argument
25 u32 mrc_size = sizeof(*cache) + cache->data_size; in next_mrc_block()
26 u8 *region_ptr = (u8 *)cache; in next_mrc_block()
38 static int is_mrc_cache(struct mrc_data_container *cache) in is_mrc_cache() argument
40 return cache && (cache->signature == MRC_DATA_SIGNATURE); in is_mrc_cache()
45 struct mrc_data_container *cache, *next; in mrccache_find_current() local
51 cache = NULL; in mrccache_find_current()
57 cache = next; in mrccache_find_current()
69 if (cache->checksum != compute_ip_checksum(cache->data, in mrccache_find_current()
70 cache->data_size)) { in mrccache_find_current()
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/rk3399_rockchip-uboot/doc/
H A DREADME.arm-caches1 Disabling I-cache:
4 Disabling D-cache:
7 Enabling I-cache:
10 Enabling D-cache:
14 - Implement enable_caches() for your platform and enable the I-cache and
15 D-cache from this function. This function is called immediately
18 Guidelines for Working with D-cache:
26 lines from the DMA buffer in the cache, subsequent cache-line replacements
29 into the cache while the DMA is going on.
33 come to the cache due to speculative memory access by the CPU. If this
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H A DREADME.mips22 writing back and invalidating cache lines. This leads to cache
24 re-initializes the cache. The more common uImage 'bootm' command does
27 [workaround] To avoid this cache incoherency,
29 2) fix dcache_disable() to do both flushing and disabling cache.
38 * Probe CPU types, I-/D-cache and TLB size etc. automatically
40 * Secondary cache support missing
48 * Due to cache initialization issues, the DRAM on board must be
49 initialized in board specific assembler language before the cache init
H A DREADME.fuse20 volatile shadow cache.
29 Read fuse words from the shadow cache.
33 Sense - i.e. read directly from the fusebox, skipping the shadow cache -
34 fuse words. This operation does not update the shadow cache.
42 irreversible. The shadow cache is updated accordingly or not, depending on
53 Override fuse words in the shadow cache.
55 The fusebox is unaffected, so following this operation, the shadow cache
57 used to get the values from the shadow cache or from the fusebox.
H A DREADME.mpc85xx-spin-table1 Spin table in cache
14 cache because this page is mapped as normal DDR. Before copying the reset page,
23 without stress DDR bus because both the code and the spin table is in cache.
26 cache coherence.
H A DREADME.POST276 "Cache test", "cache", \
277 " This test verifies the CPU cache operation.", \
307 cache - cache test
317 => diag cpu cache
320 cache - cache test
321 This test verifies the CPU cache operation.
415 This test will verify the CPU cache (L1 cache). The test will
540 To verify the data cache operation the following test scenarios will
545 - turn on the data cache
546 - switch the data cache to write-back or write-through mode
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/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S34 mov r10, #0 @ start clean at cache level 0
36 add r2, r10, r10, lsr #1 @ work out 3x current cache level
37 mov r1, r0, lsr r2 @ extract cache type bits from clidr
38 and r1, r1, #7 @ mask of the bits for current cache only
39 cmp r1, #2 @ see what cache we have at this level
40 blt skip @ skip if no cache, or just i-cache
41 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
44 and r2, r1, #7 @ extract the length of the cache lines
54 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
56 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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H A Dpsci.S197 mov r10, #0 @ start clean at cache level 0
199 add r2, r10, r10, lsr #1 @ work out 3x current cache level
200 mov r1, r0, lsr r2 @ extract cache type bits from clidr
201 and r1, r1, #7 @ mask of the bits for current cache only
202 cmp r1, #2 @ see what cache we have at this level
203 blt skip @ skip if no cache, or just i-cache
205 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
209 and r2, r1, #7 @ extract the length of the cache lines
219 orr r11, r10, r4, lsl r5 @ factor way and cache number into r11
227 add r10, r10, #2 @ increment cache number
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/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A Ddram.c22 struct mrc_data_container *cache; in prepare_mrc_cache() local
30 cache = mrccache_find_current(&entry); in prepare_mrc_cache()
31 if (!cache) in prepare_mrc_cache()
35 cache->data, cache->data_size, cache->checksum); in prepare_mrc_cache()
38 memcpy(&mrc_params->timings, cache->data, cache->data_size); in prepare_mrc_cache()
128 char *cache; in dram_init() local
154 cache = malloc(sizeof(struct mrc_timings)); in dram_init()
155 if (cache) { in dram_init()
156 memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings)); in dram_init()
157 gd->arch.mrc_output = cache; in dram_init()
/rk3399_rockchip-uboot/drivers/crypto/rockchip/
H A Dcrypto_hash_cache.c18 if (!hash_cache->cache) { in hash_cache_calc()
19 hash_cache->cache = (u8 *)memalign(CONFIG_SYS_CACHELINE_SIZE, in hash_cache_calc()
21 if (!hash_cache->cache) in hash_cache_calc()
34 memcpy(hash_cache->cache + hash_cache->cache_size, data, in hash_cache_calc()
45 hash_cache->cache, in hash_cache_calc()
60 memcpy(hash_cache->cache + hash_cache->cache_size, in hash_cache_calc()
63 ret = direct_calc(hash_cache->user_data, hash_cache->cache, in hash_cache_calc()
121 if (hash_cache->cache) in crypto_hash_cache_free()
122 free(hash_cache->cache); in crypto_hash_cache_free()
190 if (hash_cache->cache) { in crypto_hash_update_with_cache()
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/rk3399_rockchip-uboot/drivers/block/
H A Dblkcache.c22 char *cache; member
61 const char *src = node->cache + (start - node->start) * blksz; in blkcache_read()
98 free(node->cache); in blkcache_fill()
99 node->cache = 0; in blkcache_fill()
105 node->cache = 0; in blkcache_fill()
108 if (!node->cache) { in blkcache_fill()
109 node->cache = malloc(bytes); in blkcache_fill()
110 if (!node->cache) { in blkcache_fill()
124 memcpy(node->cache, buffer, bytes); in blkcache_fill()
139 free(node->cache); in blkcache_invalidate()
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/rk3399_rockchip-uboot/arch/x86/lib/fsp/
H A Dfsp_common.c89 struct mrc_data_container *cache; in fsp_prepare_mrc_cache() local
97 cache = mrccache_find_current(&entry); in fsp_prepare_mrc_cache()
98 if (!cache) in fsp_prepare_mrc_cache()
102 cache->data, cache->data_size, cache->checksum); in fsp_prepare_mrc_cache()
104 return cache->data; in fsp_prepare_mrc_cache()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7m/
H A Dcache.c64 static void get_cache_ways_sets(struct dcache_config *cache) in get_cache_ways_sets() argument
68 cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; in get_cache_ways_sets()
69 cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT; in get_cache_ways_sets()
173 struct dcache_config cache; in action_dcache_all() local
185 get_cache_ways_sets(&cache); /* Get number of ways & sets */ in action_dcache_all()
186 debug("cache: ways= %d, sets= %d\n", cache.ways + 1, cache.sets + 1); in action_dcache_all()
187 for (i = cache.sets; i >= 0; i--) { in action_dcache_all()
188 for (j = cache.ways; j >= 0; j--) { in action_dcache_all()
/rk3399_rockchip-uboot/arch/nds32/lib/
H A Dcache.c11 static inline unsigned long CACHE_SET(unsigned char cache) in CACHE_SET() argument
13 if (cache == ICACHE) in CACHE_SET()
21 static inline unsigned long CACHE_WAY(unsigned char cache) in CACHE_WAY() argument
23 if (cache == ICACHE) in CACHE_WAY()
31 static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) in CACHE_LINE_SIZE() argument
33 if (cache == ICACHE) in CACHE_LINE_SIZE()
/rk3399_rockchip-uboot/drivers/mtd/nand/
H A Dbbt.c111 BITS_PER_LONG) * sizeof(*nand->bbt.cache); in nanddev_read_bbt()
120 if (!nand->bbt.cache) in nanddev_read_bbt()
180 memcpy(nand->bbt.cache, data_buf, nbytes); in nanddev_read_bbt()
193 memcpy(temp_buf, nand->bbt.cache, nbytes); in nanddev_read_bbt()
194 memcpy(nand->bbt.cache, data_buf, nbytes); in nanddev_read_bbt()
205 memcpy(nand->bbt.cache, temp_buf, nbytes); in nanddev_read_bbt()
223 BITS_PER_LONG) * sizeof(*nand->bbt.cache); in nanddev_write_bbt()
233 if (!nand->bbt.cache) in nanddev_write_bbt()
256 memcpy(data_buf, nand->bbt.cache, nbytes); in nanddev_write_bbt()
312 memset(nand->bbt.cache, 0, nwords * sizeof(*nand->bbt.cache)); in nanddev_bbt_format()
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/rk3399_rockchip-uboot/fs/reiserfs/
H A Dreiserfs.c273 char *cache; in reiserfs_mount() local
349 cache = ROOT; in reiserfs_mount()
350 INFO->tree_depth = __le16_to_cpu(BLOCKHEAD (cache)->blk_level); in reiserfs_mount()
395 char* cache = CACHE(depth); in read_tree_node() local
403 return cache; in read_tree_node()
406 cache = CACHE(num_cached); in read_tree_node()
412 if (! block_read (blockNr, 0, INFO->blocksize, cache)) in read_tree_node()
415 if (__le16_to_cpu(BLOCKHEAD (cache)->blk_level) != depth) in read_tree_node()
422 return cache; in read_tree_node()
433 char *cache; in next_key() local
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/rk3399_rockchip-uboot/fs/yaffs2/
H A Dyaffs_guts.c201 if (dev->cache[i].data == buffer) in yaffs_is_managed_tmp_buffer()
1371 struct yaffs_cache *cache; in yaffs_obj_cache_dirty() local
1375 cache = &dev->cache[i]; in yaffs_obj_cache_dirty()
1376 if (cache->object == obj && cache->dirty) in yaffs_obj_cache_dirty()
1388 struct yaffs_cache *cache; in yaffs_flush_file_cache() local
1395 cache = NULL; in yaffs_flush_file_cache()
1399 if (dev->cache[i].object == obj && in yaffs_flush_file_cache()
1400 dev->cache[i].dirty) { in yaffs_flush_file_cache()
1401 if (!cache || in yaffs_flush_file_cache()
1402 dev->cache[i].chunk_id < lowest) { in yaffs_flush_file_cache()
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/rk3399_rockchip-uboot/arch/arm/dts/
H A Duniphier-pro5.dtsi25 next-level-cache = <&l2>;
35 next-level-cache = <&l2>;
137 l2: l2-cache@500c0000 {
138 compatible = "socionext,uniphier-system-cache";
142 cache-unified;
143 cache-size = <(2 * 1024 * 1024)>;
144 cache-sets = <512>;
145 cache-line-size = <128>;
146 cache-level = <2>;
147 next-level-cache = <&l3>;
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/rk3399_rockchip-uboot/board/freescale/bsc9131rdb/
H A DREADME10 L2 cache
11 . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
46 . 32-Kbyte L1 instruction cache
47 . 32-Kbyte L1 data cache
48 . 256-Kbyte L2 cache/L2 memory/L2 stash
54 . 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
55 . 32 Kbyte 8-way level 1 data cache (L1 DCache)
56 . 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
/rk3399_rockchip-uboot/arch/x86/dts/
H A Dbaytrail_som-db5800-som-6867.dts204 rw-mrc-cache {
205 label = "rw-mrc-cache";
216 use-lvl-write-cache;
224 use-lvl-write-cache;
232 use-lvl-write-cache;
240 use-lvl-write-cache;
248 use-lvl-write-cache;
256 use-lvl-write-cache;
H A Dbayleybay.dts181 rw-mrc-cache {
182 label = "rw-mrc-cache";
193 use-lvl-write-cache;
201 use-lvl-write-cache;
209 use-lvl-write-cache;
217 use-lvl-write-cache;
225 use-lvl-write-cache;
233 use-lvl-write-cache;
H A Dconga-qeval20-qa3-e3845.dts191 rw-mrc-cache {
192 label = "rw-mrc-cache";
203 use-lvl-write-cache;
211 use-lvl-write-cache;
219 use-lvl-write-cache;
227 use-lvl-write-cache;
235 use-lvl-write-cache;
243 use-lvl-write-cache;
/rk3399_rockchip-uboot/arch/powerpc/lib/
H A DMakefile21 obj-y += cache.o time.o
33 obj-y += cache.o
/rk3399_rockchip-uboot/arch/nds32/cpu/n1213/
H A Dstart.S25 #define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
26 #define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
28 #define DCAC_MEM_KBF_DWAY (0x07<<3) ! D cache ways
29 #define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
45 #define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
46 #define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
354 ! $t1= bit width of I cache line size(ISZ)
358 sll $t5, $t4, $t1 ! get $t5 cache line size
365 sll $p1, $p1, $t3 ! GET the total cache size
389 ! $t1= bit width of D cache line size(DSZ)
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/rk3399_rockchip-uboot/doc/device-tree-bindings/cpu/
H A Dnios2.txt15 - dcache-line-size: Contains data cache line size.
17 - dcache-size: Contains data cache size.
18 - icache-size: Contains instruction cache size.

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