1*bcae80e9SThomas Chou* Nios II Processor Binding 2*bcae80e9SThomas Chou 3*bcae80e9SThomas ChouThis binding specifies what properties available in the device tree 4*bcae80e9SThomas Chourepresentation of a Nios II Processor Core. 5*bcae80e9SThomas Chou 6*bcae80e9SThomas ChouUsers can use sopc2dts tool for generating device tree sources (dts) from a 7*bcae80e9SThomas ChouQsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts 8*bcae80e9SThomas Chou 9*bcae80e9SThomas ChouRequired properties: 10*bcae80e9SThomas Chou 11*bcae80e9SThomas Chou- compatible: Compatible property value should be "altr,nios2-1.0" or 12*bcae80e9SThomas Chou "altr,nios2-1.1". 13*bcae80e9SThomas Chou- reg: Contains CPU index. 14*bcae80e9SThomas Chou- clock-frequency: Contains the clock frequency for CPU, in Hz. 15*bcae80e9SThomas Chou- dcache-line-size: Contains data cache line size. 16*bcae80e9SThomas Chou- icache-line-size: Contains instruction line size. 17*bcae80e9SThomas Chou- dcache-size: Contains data cache size. 18*bcae80e9SThomas Chou- icache-size: Contains instruction cache size. 19*bcae80e9SThomas Chou- altr,reset-addr: Specifies CPU reset address 20*bcae80e9SThomas Chou- altr,exception-addr: Specifies CPU exception address 21*bcae80e9SThomas Chou 22*bcae80e9SThomas ChouOptional properties: 23*bcae80e9SThomas Chou- altr,has-initda: Specifies CPU support initda instruction, should be 1. 24*bcae80e9SThomas Chou- altr,has-mmu: Specifies CPU support MMU support. 25*bcae80e9SThomas Chou- altr,has-mul: Specifies CPU hardware multipy support. 26*bcae80e9SThomas Chou- altr,has-div: Specifies CPU hardware divide support 27*bcae80e9SThomas Chou- altr,implementation: Nios II core implementation, this should be "fast"; 28*bcae80e9SThomas Chou 29*bcae80e9SThomas ChouExample: 30*bcae80e9SThomas Chou 31*bcae80e9SThomas Choucpu@0x0 { 32*bcae80e9SThomas Chou device_type = "cpu"; 33*bcae80e9SThomas Chou compatible = "altr,nios2-1.0"; 34*bcae80e9SThomas Chou reg = <0>; 35*bcae80e9SThomas Chou interrupt-controller; 36*bcae80e9SThomas Chou #interrupt-cells = <1>; 37*bcae80e9SThomas Chou clock-frequency = <125000000>; 38*bcae80e9SThomas Chou dcache-line-size = <32>; 39*bcae80e9SThomas Chou icache-line-size = <32>; 40*bcae80e9SThomas Chou dcache-size = <32768>; 41*bcae80e9SThomas Chou icache-size = <32768>; 42*bcae80e9SThomas Chou altr,implementation = "fast"; 43*bcae80e9SThomas Chou altr,pid-num-bits = <8>; 44*bcae80e9SThomas Chou altr,tlb-num-ways = <16>; 45*bcae80e9SThomas Chou altr,tlb-num-entries = <128>; 46*bcae80e9SThomas Chou altr,tlb-ptr-sz = <7>; 47*bcae80e9SThomas Chou altr,has-div = <1>; 48*bcae80e9SThomas Chou altr,has-mul = <1>; 49*bcae80e9SThomas Chou altr,reset-addr = <0xc2800000>; 50*bcae80e9SThomas Chou altr,fast-tlb-miss-addr = <0xc7fff400>; 51*bcae80e9SThomas Chou altr,exception-addr = <0xd0000020>; 52*bcae80e9SThomas Chou altr,has-initda = <1>; 53*bcae80e9SThomas Chou altr,has-mmu = <1>; 54*bcae80e9SThomas Chou}; 55