Home
last modified time | relevance | path

Searched refs:UPDATE (Results 1 – 20 of 20) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_hdmitx.h30 #define NOT_RST_ANALOG(x) UPDATE(x, 6, 6)
32 #define NOT_RST_DIGITAL(x) UPDATE(x, 5, 5)
34 #define REG_CLK_INV(x) UPDATE(x, 4, 4)
36 #define VCLK_INV(x) UPDATE(x, 3, 3)
38 #define REG_CLK_SOURCE(x) UPDATE(x, 2, 2)
40 #define PWR_OFF(x) UPDATE(x, 1, 1)
42 #define INT_POL(x) UPDATE(x, 0, 0)
46 #define VIDEO_INPUT_SDR_RGB444 UPDATE(0x0, 3, 1)
47 #define VIDEO_INPUT_DDR_RGB444 UPDATE(0x5, 3, 1)
48 #define VIDEO_INPUT_DDR_YCBCR422 UPDATE(0x6, 3, 1)
[all …]
H A Drk628_dsi.h20 #define TO_CLK_DIVISION(x) UPDATE(x, 15, 8)
21 #define TX_ESC_CLK_DIVISION(x) UPDATE(x, 7, 0)
23 #define DPI_VID(x) UPDATE(x, 1, 0)
26 #define DPI_COLOR_CODING(x) UPDATE(x, 3, 0)
34 #define OUTVACT_LPCMD_TIME(x) UPDATE(x, 23, 16)
35 #define INVACT_LPCMD_TIME(x) UPDATE(x, 7, 0)
44 #define CMD_VIDEO_MODE(x) UPDATE(x, 0, 0)
55 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0)
57 #define VID_PKT_SIZE(x) UPDATE(x, 13, 0)
61 #define VID_HSA_TIME(x) UPDATE(x, 11, 0)
[all …]
H A Drk628_combtxphy.h16 #define SW_TX_IDLE(x) UPDATE(x, 29, 20)
18 #define SW_TX_PD(x) UPDATE(x, 17, 8)
20 #define SW_BUS_WIDTH_7BIT UPDATE(0x3, 6, 5)
21 #define SW_BUS_WIDTH_8BIT UPDATE(0x2, 6, 5)
22 #define SW_BUS_WIDTH_9BIT UPDATE(0x1, 6, 5)
23 #define SW_BUS_WIDTH_10BIT UPDATE(0x0, 6, 5)
39 #define SW_RATE(x) UPDATE(x, 26, 24)
40 #define SW_REF_DIV(x) UPDATE(x, 20, 16)
41 #define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10)
42 #define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0)
[all …]
H A Drk628_hdmirx.h22 #define HOT_PLUG_DETECT(x) UPDATE(x, 0, 0)
37 #define SEL_PIXCLKSRC(x) UPDATE(x, 19, 18)
50 #define PREAMBLE_CNT_LIMIT(x) UPDATE(x, 31, 27)
52 #define OESSCTL3_THR(x) UPDATE(x, 20, 19)
54 #define SPIKE_FILTER_EN(x) UPDATE(x, 18, 18)
56 #define DVI_MODE_HYST(x) UPDATE(x, 17, 13)
58 #define HDMI_MODE_HYST(x) UPDATE(x, 12, 8)
60 #define HDMI_MODE(x) UPDATE(x, 7, 6)
62 #define GB_DET(x) UPDATE(x, 5, 4)
64 #define EESS_OESS(x) UPDATE(x, 3, 2)
[all …]
H A Drk628_gvi.h46 #define SYS_CTRL0_LANE_NUM(x) UPDATE(x, 7, 4)
48 #define SYS_CTRL0_BYTE_MODE(x) UPDATE(x, 9, 8)
50 #define SYS_CTRL0_SECTION_NUM(x) UPDATE(x, 11, 10)
60 #define SYS_CTRL0_GVI_GN_EN(x) UPDATE(x, 19, 16)
75 #define SYS_CTRL1_COLOR_DEPTH(x) UPDATE(x, 3, 0)
89 #define SYS_CTRL2_AFIFO_READ_THOLD(x) UPDATE(x, 7, 0)
91 #define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD(x) UPDATE(x, 23, 16)
93 #define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD(x) UPDATE(x, 31, 24)
97 #define SYS_CTRL3_LANE0_SEL(x) UPDATE(x, 2, 0)
99 #define SYS_CTRL3_LANE1_SEL(x) UPDATE(x, 6, 4)
[all …]
H A Drk628.h24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
30 #define SW_VSYNC_POL(x) UPDATE(x, 26, 26)
32 #define SW_HSYNC_POL(x) UPDATE(x, 25, 25)
34 #define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22)
36 #define SW_EDID_MODE(x) UPDATE(x, 21, 21)
38 #define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10)
42 #define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8)
44 #define SW_OUTPUT_MODE(x) UPDATE(x, 5, 3)
47 #define SW_OUTPUT_RGB_MODE(x) UPDATE(x, 7, 6)
49 #define SW_HDMITX_EN(x) UPDATE(x, 5, 5)
[all …]
H A Drk628_dsi.c22 #define HSFREQRANGE(x) UPDATE(x, 6, 1)
/rk3399_rockchip-uboot/drivers/video/rk_eink/
H A Drk_ebc_tcon.c35 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
65 #define DSP_HTOTAL(x) UPDATE(x, 27, 16)
66 #define DSP_HS_END(x) UPDATE(x, 7, 0)
67 #define DSP_HACT_END(x) UPDATE(x, 26, 16)
68 #define DSP_HACT_ST(x) UPDATE(x, 7, 0)
69 #define DSP_VTOTAL(x) UPDATE(x, 26, 16)
70 #define DSP_VS_END(x) UPDATE(x, 7, 0)
71 #define DSP_VACT_END(x) UPDATE(x, 26, 16)
72 #define DSP_VACT_ST(x) UPDATE(x, 7, 0)
73 #define DSP_HEIGHT(x) UPDATE(x, 26, 16)
[all …]
/rk3399_rockchip-uboot/drivers/video/drm/
H A Drk618_dsi.c28 #define TO_CLK_DIVIDSION(x) UPDATE(x, 15, 8)
29 #define TX_ESC_CLK_DIVIDSION(x) UPDATE(x, 7, 0)
37 #define DPI_COLOR_CODING(x) UPDATE(x, 4, 2)
38 #define DPI_VID(x) UPDATE(x, 1, 0)
40 #define GEN_VID_RX(x) UPDATE(x, 6, 5)
57 #define VID_MODE_TYPE(x) UPDATE(x, 2, 1)
60 #define NULL_PKT_SIZE(x) UPDATE(x, 30, 21)
61 #define NUM_CHUNKS(x) UPDATE(x, 20, 11)
62 #define VID_PKT_SIZE(x) UPDATE(x, 10, 0)
80 #define HLINE_TIME(x) UPDATE(x, 31, 18)
[all …]
H A Dinno_video_combo_phy.c24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
49 #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
50 #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
63 #define REG_FBDIV_HI(x) UPDATE(x, 5, 5)
65 #define REG_PREDIV(x) UPDATE(x, 4, 0)
68 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
71 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
73 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
76 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
78 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0)
[all …]
H A Dsamsung_mipi_dcphy.c28 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
36 #define I_MUX_SEL(x) UPDATE(x, 6, 5)
41 #define S(x) UPDATE(x, 10, 8)
43 #define P(x) UPDATE(x, 5, 0)
47 #define M(x) UPDATE(x, 9, 0)
50 #define MRR(x) UPDATE(x, 13, 8)
52 #define MFR(x) UPDATE(x, 7, 0)
60 #define PLL_LOCK_CNT(x) UPDATE(x, 15, 0)
62 #define PLL_STB_CNT(x) UPDATE(x, 15, 0)
70 #define T_PHY_READY(x) UPDATE(x, 15, 0)
[all …]
H A Dinno_mipi_phy.c26 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) macro
55 #define FBDIV_HI(x) UPDATE(x, 5, 5)
57 #define PREDIV(x) UPDATE(x, 4, 0)
60 #define FBDIV_LO(x) UPDATE(x, 7, 0)
69 #define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
72 #define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
90 #define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
93 #define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
96 #define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
131 #define T_LPX(x) UPDATE(x, 5, 0)
[all …]
H A Drockchip-inno-hdmi-phy.c30 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
51 #define AUDO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
53 #define AUDO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
77 #define TMDS_DRIVER_ENABLE UPDATE(0xf, 3, 0)
82 #define PRE_PLL_FB_DIV_8(x) UPDATE(x, 7, 7)
85 #define PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)
87 #define PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
89 #define PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
93 #define PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
96 #define PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
[all …]
H A Ddw_mipi_dsi2.c32 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) macro
37 #define CMD_TX_MODE(x) UPDATE(x, 24, 24)
59 #define TO_HSTX(x) UPDATE(x, 15, 0)
61 #define TO_HSTXRDY(x) UPDATE(x, 15, 0)
63 #define TO_LPRXRDY(x) UPDATE(x, 15, 0)
65 #define TO_LPTXRDY(x) UPDATE(x, 15, 0)
67 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0)
69 #define TO_LPTXULPS(x) UPDATE(x, 15, 0)
71 #define TO_BTA(x) UPDATE(x, 15, 0)
74 #define PPI_WIDTH(x) UPDATE(x, 9, 8)
[all …]
H A Dphy-rockchip-samsung-hdptx-hdmi.c26 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
49 #define LCPLL_EN(x) UPDATE(x, 4, 4)
51 #define LCPLL_LCVCO_MODE_EN(x) UPDATE(x, 4, 4)
75 #define LCPLL_PI_EN(x) UPDATE(x, 5, 5)
77 #define LCPLL_100M_CLK_EN(x) UPDATE(x, 0, 0)
97 #define LCPLL_SDC_N(x) UPDATE(x, 3, 1)
100 #define LCPLL_SDC_NUMBERATOR(x) UPDATE(x, 5, 0)
103 #define LCPLL_SDC_DENOMINATOR(x) UPDATE(x, 7, 2)
156 #define ROPLL_SDM_EN(x) UPDATE(x, 6, 6)
168 #define ROPLL_SDM_NUM_SIGN_RBR(x) UPDATE(x, 3, 3)
[all …]
H A Drk618.h14 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) macro
H A Ddw_mipi_dsi.c28 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) macro
63 #define DBI_VCID(x) UPDATE(x, 1, 0)
181 #define PHY_TESTDIN(x) UPDATE(x, 7, 0)
192 #define HSFREQRANGE(x) UPDATE(x, 6, 1)
194 #define INPUT_DIV(x) UPDATE(x, 6, 0)
196 #define FEEDBACK_DIV_LO(x) UPDATE(x, 4, 0)
197 #define FEEDBACK_DIV_HI(x) (BIT(7) | UPDATE(x, 3, 0))
/rk3399_rockchip-uboot/drivers/power/domain/
H A Dtegra186-power-domain.c13 #define UPDATE BIT(0) macro
24 req.logic_state = UPDATE | on_state; in tegra186_power_domain_common()
25 req.sram_state = UPDATE | on_state; in tegra186_power_domain_common()
31 req.clock_state = UPDATE; in tegra186_power_domain_common()
/rk3399_rockchip-uboot/drivers/power/charge/
H A Dcps5601x_charger.c26 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
57 #define EN_TERM_ENABLE(x) UPDATE(x, 6, 6)
104 #define WATCHDOG_TIME(x) UPDATE(x, 7, 6)
108 #define WD_RST(x) UPDATE(x, 5, 5)
110 #define EN_CHG(x) UPDATE(x, 3, 3)
115 #define EN_OTG(x) UPDATE(x, 3, 3)
123 #define EN_TS_IGNORE(x) UPDATE(x, 0, 0)
/rk3399_rockchip-uboot/lib/zlib/
H A Dinflate.c152 # define UPDATE(check, buf, len) \ macro
155 # define UPDATE(check, buf, len) adler32(check, buf, len) macro
859 UPDATE(state->check, put - out, out); in inflate()
921 UPDATE(state->check, strm->next_out - out, out); in inflate()