1*117fdc89SWyon Bi /* SPDX-License-Identifier: GPL-2.0+ */ 2*117fdc89SWyon Bi /* 3*117fdc89SWyon Bi * (C) Copyright 2008-2018 Fuzhou Rockchip Electronics Co., Ltd 4*117fdc89SWyon Bi */ 5*117fdc89SWyon Bi 6*117fdc89SWyon Bi #ifndef _RK618_H_ 7*117fdc89SWyon Bi #define _RK618_H_ 8*117fdc89SWyon Bi 9*117fdc89SWyon Bi #include <clk.h> 10*117fdc89SWyon Bi #include <dm/device.h> 11*117fdc89SWyon Bi #include <power/regulator.h> 12*117fdc89SWyon Bi #include <asm/gpio.h> 13*117fdc89SWyon Bi 14*117fdc89SWyon Bi #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 15*117fdc89SWyon Bi #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK(h, l) << 16)) 16*117fdc89SWyon Bi 17*117fdc89SWyon Bi #define RK618_FRC_REG 0x0054 18*117fdc89SWyon Bi #define FRC_DEN_INV HIWORD_UPDATE(1, 6, 6) 19*117fdc89SWyon Bi #define FRC_SYNC_INV HIWORD_UPDATE(1, 5, 5) 20*117fdc89SWyon Bi #define FRC_DCLK_INV HIWORD_UPDATE(1, 4, 4) 21*117fdc89SWyon Bi #define FRC_OUT_ZERO HIWORD_UPDATE(1, 3, 3) 22*117fdc89SWyon Bi #define FRC_OUT_MODE_RGB666 HIWORD_UPDATE(1, 2, 2) 23*117fdc89SWyon Bi #define FRC_OUT_MODE_RGB888 HIWORD_UPDATE(0, 2, 2) 24*117fdc89SWyon Bi #define FRC_DITHER_MODE_HI_FRC HIWORD_UPDATE(1, 1, 1) 25*117fdc89SWyon Bi #define FRC_DITHER_MODE_FRC HIWORD_UPDATE(0, 1, 1) 26*117fdc89SWyon Bi #define FRC_DITHER_ENABLE HIWORD_UPDATE(1, 0, 0) 27*117fdc89SWyon Bi #define FRC_DITHER_DISABLE HIWORD_UPDATE(0, 0, 0) 28*117fdc89SWyon Bi #define RK618_LVDS_CON 0x0084 29*117fdc89SWyon Bi #define LVDS_CON_START_PHASE(x) HIWORD_UPDATE(x, 14, 14) 30*117fdc89SWyon Bi #define LVDS_DCLK_INV HIWORD_UPDATE(1, 13, 13) 31*117fdc89SWyon Bi #define LVDS_CON_CHADS_10PF HIWORD_UPDATE(3, 12, 11) 32*117fdc89SWyon Bi #define LVDS_CON_CHADS_5PF HIWORD_UPDATE(2, 12, 11) 33*117fdc89SWyon Bi #define LVDS_CON_CHADS_7PF HIWORD_UPDATE(1, 12, 11) 34*117fdc89SWyon Bi #define LVDS_CON_CHADS_3PF HIWORD_UPDATE(0, 12, 11) 35*117fdc89SWyon Bi #define LVDS_CON_CHA1TTL_ENABLE HIWORD_UPDATE(1, 10, 10) 36*117fdc89SWyon Bi #define LVDS_CON_CHA1TTL_DISABLE HIWORD_UPDATE(0, 10, 10) 37*117fdc89SWyon Bi #define LVDS_CON_CHA0TTL_ENABLE HIWORD_UPDATE(1, 9, 9) 38*117fdc89SWyon Bi #define LVDS_CON_CHA0TTL_DISABLE HIWORD_UPDATE(0, 9, 9) 39*117fdc89SWyon Bi #define LVDS_CON_CHA1_POWER_UP HIWORD_UPDATE(1, 8, 8) 40*117fdc89SWyon Bi #define LVDS_CON_CHA1_POWER_DOWN HIWORD_UPDATE(0, 8, 8) 41*117fdc89SWyon Bi #define LVDS_CON_CHA0_POWER_UP HIWORD_UPDATE(1, 7, 7) 42*117fdc89SWyon Bi #define LVDS_CON_CHA0_POWER_DOWN HIWORD_UPDATE(0, 7, 7) 43*117fdc89SWyon Bi #define LVDS_CON_CBG_POWER_UP HIWORD_UPDATE(1, 6, 6) 44*117fdc89SWyon Bi #define LVDS_CON_CBG_POWER_DOWN HIWORD_UPDATE(0, 6, 6) 45*117fdc89SWyon Bi #define LVDS_CON_PLL_POWER_DOWN HIWORD_UPDATE(1, 5, 5) 46*117fdc89SWyon Bi #define LVDS_CON_PLL_POWER_UP HIWORD_UPDATE(0, 5, 5) 47*117fdc89SWyon Bi #define LVDS_CON_START_SEL_EVEN_PIXEL HIWORD_UPDATE(1, 4, 4) 48*117fdc89SWyon Bi #define LVDS_CON_START_SEL_ODD_PIXEL HIWORD_UPDATE(0, 4, 4) 49*117fdc89SWyon Bi #define LVDS_CON_CHASEL_DOUBLE_CHANNEL HIWORD_UPDATE(1, 3, 3) 50*117fdc89SWyon Bi #define LVDS_CON_CHASEL_SINGLE_CHANNEL HIWORD_UPDATE(0, 3, 3) 51*117fdc89SWyon Bi #define LVDS_CON_MSBSEL_D7 HIWORD_UPDATE(1, 2, 2) 52*117fdc89SWyon Bi #define LVDS_CON_MSBSEL_D0 HIWORD_UPDATE(0, 2, 2) 53*117fdc89SWyon Bi #define LVDS_CON_SELECT(x) HIWORD_UPDATE(x, 1, 0) 54*117fdc89SWyon Bi #define LVDS_CON_SELECT_6BIT_MODE HIWORD_UPDATE(3, 1, 0) 55*117fdc89SWyon Bi #define LVDS_CON_SELECT_8BIT_MODE_3 HIWORD_UPDATE(2, 1, 0) 56*117fdc89SWyon Bi #define LVDS_CON_SELECT_8BIT_MODE_2 HIWORD_UPDATE(1, 1, 0) 57*117fdc89SWyon Bi #define LVDS_CON_SELECT_8BIT_MODE_1 HIWORD_UPDATE(0, 1, 0) 58*117fdc89SWyon Bi 59*117fdc89SWyon Bi struct rk618 { 60*117fdc89SWyon Bi struct udevice *dev; 61*117fdc89SWyon Bi struct udevice *power_supply; 62*117fdc89SWyon Bi struct gpio_desc enable_gpio; 63*117fdc89SWyon Bi struct gpio_desc reset_gpio; 64*117fdc89SWyon Bi struct clk clkin; 65*117fdc89SWyon Bi }; 66*117fdc89SWyon Bi 67*117fdc89SWyon Bi int rk618_i2c_write(struct rk618 *rk618, u16 reg, u32 val); 68*117fdc89SWyon Bi int rk618_i2c_read(struct rk618 *rk618, u16 reg, u32 *val); 69*117fdc89SWyon Bi void rk618_frc_dither_disable(struct rk618 *rk618); 70*117fdc89SWyon Bi void rk618_frc_dither_enable(struct rk618 *rk618); 71*117fdc89SWyon Bi void rk618_frc_dclk_invert(struct rk618 *rk618); 72*117fdc89SWyon Bi 73*117fdc89SWyon Bi #endif 74