Searched refs:PAD_CTL_SRE_SLOW (Results 1 – 16 of 16) sorted by relevance
16 #define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \22 #define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \28 #define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \40 PAD_CTL_ODE | PAD_CTL_SRE_SLOW)
44 PAD_CTL_SRE_SLOW \146 PAD_CTL_SRE_SLOW \196 PAD_CTL_SRE_SLOW \206 PAD_CTL_SRE_SLOW \
90 PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)91 #define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)106 #define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
31 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \34 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
105 #define PAD_CTL_SRE_SLOW (0x1 << 2) macro207 #define PAD_CTL_SRE_SLOW (0 << 0) macro
86 #define PAD_CTL_SRE_SLOW (1 << 2) macro
58 PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW)); in setup_iomux_lcd()
32 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \40 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
38 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \49 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
70 PAD_CTL_SRE_SLOW)74 PAD_CTL_SRE_SLOW)78 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
71 PAD_CTL_SRE_SLOW)75 PAD_CTL_SRE_SLOW)79 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
43 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
62 PAD_CTL_SRE_SLOW)66 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
31 PAD_CTL_SRE_SLOW)
324 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
125 PAD_CTL_SRE_SLOW = 0x0 << 0, enumerator