| /rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/src/ |
| H A D | ddrphy_phyinit_softsetmb.c | 29 uint32_t value) in ddrphy_phyinit_softsetmb() argument
34 assert(value <= UINT16_MAX); in ddrphy_phyinit_softsetmb()
36 assert(value <= UINT8_MAX); in ddrphy_phyinit_softsetmb()
41 mb_ddr_1d->pstate = (uint8_t)value; in ddrphy_phyinit_softsetmb()
44 mb_ddr_1d->pllbypassen = (uint8_t)value; in ddrphy_phyinit_softsetmb()
47 mb_ddr_1d->dramfreq = (uint16_t)value; in ddrphy_phyinit_softsetmb()
50 mb_ddr_1d->dfifreqratio = (uint8_t)value; in ddrphy_phyinit_softsetmb()
53 mb_ddr_1d->bpznresval = (uint8_t)value; in ddrphy_phyinit_softsetmb()
56 mb_ddr_1d->phyodtimpedance = (uint8_t)value; in ddrphy_phyinit_softsetmb()
59 mb_ddr_1d->phydrvimpedance = (uint8_t)value; in ddrphy_phyinit_softsetmb()
[all …]
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/include/ |
| H A D | s10_memory_controller.h | 23 #define S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \ argument
24 (((value) & 0x00000060) >> 5)
73 #define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18) argument
74 #define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) argument
75 #define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0) argument
76 #define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) argument
79 #define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6) argument
80 #define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24) argument
81 #define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18) argument
82 #define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6) argument
[all …]
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| /rk3399_ARM-atf/lib/extensions/idte/ |
| H A D | idte3.c | 117 u_register_t value = 0ULL; in handle_idreg_trap() local
127 value = perworld_reg->id_aa64pfr0_el1; in handle_idreg_trap()
130 value = perworld_reg->id_aa64pfr1_el1; in handle_idreg_trap()
133 value = perworld_reg->id_aa64pfr2_el1; in handle_idreg_trap()
136 value = perworld_reg->id_aa64smfr0_el1; in handle_idreg_trap()
139 value = perworld_reg->id_aa64isar0_el1; in handle_idreg_trap()
142 value = perworld_reg->id_aa64isar1_el1; in handle_idreg_trap()
145 value = perworld_reg->id_aa64isar2_el1; in handle_idreg_trap()
148 value = perworld_reg->id_aa64isar3_el1; in handle_idreg_trap()
151 value = perworld_reg->id_aa64mmfr0_el1; in handle_idreg_trap()
[all …]
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/include/ |
| H A D | agilex5_memory_controller.h | 26 #define AGX_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) (((value) & 0x00000060) >> 5) argument
74 #define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18) argument
75 #define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) argument
76 #define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0) argument
77 #define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) argument
80 #define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6) argument
81 #define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24) argument
82 #define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18) argument
83 #define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6) argument
86 #define CALTIMING3_WR_TO_RD_DIFF_CHIP(value) (((value) & 0x0003f000) >> 12) argument
[all …]
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| /rk3399_ARM-atf/plat/intel/soc/agilex/include/ |
| H A D | agilex_memory_controller.h | 25 #define AGX_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \ argument
26 (((value) & 0x00000060) >> 5)
74 #define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18) argument
75 #define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) argument
76 #define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0) argument
77 #define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) argument
80 #define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6) argument
81 #define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24) argument
82 #define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18) argument
83 #define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6) argument
[all …]
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| /rk3399_ARM-atf/drivers/cadence/combo_phy/ |
| H A D | cdns_combo_phy.c | 24 uint32_t value = 0U; in cdns_sdmmc_write_phy_reg() local
27 value = mmio_read_32(phy_reg_addr); in cdns_sdmmc_write_phy_reg()
28 value &= ~PHY_REG_ADDR_MASK; in cdns_sdmmc_write_phy_reg()
29 value |= phy_reg_addr_value; in cdns_sdmmc_write_phy_reg()
30 mmio_write_32(phy_reg_addr, value); in cdns_sdmmc_write_phy_reg()
38 value &= ~PHY_REG_DATA_MASK; in cdns_sdmmc_write_phy_reg()
39 value |= phy_reg_data_value; in cdns_sdmmc_write_phy_reg()
40 mmio_write_32(phy_reg_data, value); in cdns_sdmmc_write_phy_reg()
52 uint32_t value = 0; in cdns_sd_card_detect() local
56 value = mmio_read_32(SDMMC_CDN(SRS09)); in cdns_sd_card_detect()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/ |
| H A D | apusys_security_ctrl_plat.c | 22 uint32_t value = mmio_read_32(SEC_CTRL_SIDE_BAND); in sec_sideband_init() local
24 value = bits_set(value, SEC_CTRL_NARE_DOMAIN, SEC_CTRL_DOMAIN_MASK, in sec_sideband_init()
26 value = bits_set(value, SEC_CTRL_NARE_NS, SEC_CTRL_NS_MASK, SEC_CTRL_NARE_NS_SHF); in sec_sideband_init()
27 value = bits_set(value, SEC_CTRL_SARE0_DOMAIN, SEC_CTRL_DOMAIN_MASK, in sec_sideband_init()
29 value = bits_set(value, SEC_CTRL_SARE0_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE0_NS_SHF); in sec_sideband_init()
30 value = bits_set(value, SEC_CTRL_SARE1_DOMAIN, SEC_CTRL_DOMAIN_MASK, in sec_sideband_init()
32 value = bits_set(value, SEC_CTRL_SARE1_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE1_NS_SHF); in sec_sideband_init()
34 mmio_write_32(SEC_CTRL_SIDE_BAND, value); in sec_sideband_init()
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| /rk3399_ARM-atf/docs/components/fconf/ |
| H A D | tb_fw_bindings.rst | 14 - value type: <string>
19 - value type: <string>
23 - value type: <string>
27 - value type: <string>
31 - value type: <string>
35 - value type: <string>
39 - value type: <string>
43 - value type: <string>
47 - value type: <string>
51 - value type: <string>
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/ptp3/ |
| H A D | ptp3_common.c | 17 unsigned int i, addr, value; in ptp3_init() local
30 value = ptp3_cfg2[i][PTP3_CFG_VALUE]; in ptp3_init()
32 mmio_write_32(addr, value); in ptp3_init()
39 value = ptp3_cfg2[i][PTP3_CFG_VALUE] + 0x5E0; in ptp3_init()
41 value = ptp3_cfg2[i][PTP3_CFG_VALUE]; in ptp3_init()
43 mmio_write_32(addr, value); in ptp3_init()
49 value = ptp3_cfg3[PTP3_CFG_VALUE]; in ptp3_init()
52 value = ptp3_cfg3_ext[PTP3_CFG_VALUE]; in ptp3_init()
54 mmio_write_32(addr, value & PTP3_CFG3_MASK1); in ptp3_init()
55 mmio_write_32(addr, value & PTP3_CFG3_MASK2); in ptp3_init()
[all …]
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| /rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/ |
| H A D | pm_api_ioctl.c | 104 uint32_t value) in pm_ioctl_config_boot_addr() argument
118 if (value == PM_RPU_BOOTMEM_LOVEC) { in pm_ioctl_config_boot_addr()
120 } else if (value == PM_RPU_BOOTMEM_HIVEC) { in pm_ioctl_config_boot_addr()
141 static enum pm_ret_status pm_ioctl_config_tcm_comb(uint32_t value) in pm_ioctl_config_tcm_comb() argument
148 if (value == PM_RPU_TCM_SPLIT) { in pm_ioctl_config_tcm_comb()
150 } else if (value == PM_RPU_TCM_COMB) { in pm_ioctl_config_tcm_comb()
176 uint32_t value, in pm_ioctl_set_tapdelay_bypass() argument
181 if ((((value != PM_TAPDELAY_BYPASS_ENABLE) && in pm_ioctl_set_tapdelay_bypass()
182 (value != PM_TAPDELAY_BYPASS_DISABLE)) || (type >= PM_TAPDELAY_MAX))) { in pm_ioctl_set_tapdelay_bypass()
186 value << type, flag); in pm_ioctl_set_tapdelay_bypass()
[all …]
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| H A D | zynqmp_pm_svc_main.c | 151 uint32_t value; in zynqmp_sgi7_irq() local
169 pm_mmio_read(PMU_GLOBAL_GEN_STORAGE4, &value, SECURE); in zynqmp_sgi7_irq()
170 value = (value & RESTART_SCOPE_MASK) >> RESTART_SCOPE_SHIFT; in zynqmp_sgi7_irq()
171 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, value, SECURE); in zynqmp_sgi7_irq()
386 uint32_t value = 0U; in pm_smc_handler() local
388 ret = pm_fpga_get_status(&value, security_flag); in pm_smc_handler()
389 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32))); in pm_smc_handler()
408 uint32_t value = 0U; in pm_smc_handler() local
411 pm_arg[3], &value, security_flag); in pm_smc_handler()
412 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32))); in pm_smc_handler()
[all …]
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| /rk3399_ARM-atf/include/lib/ |
| H A D | mmio.h | 12 static inline void mmio_write_8(uintptr_t addr, uint8_t value) in mmio_write_8() argument
14 *(volatile uint8_t*)addr = value; in mmio_write_8()
22 static inline void mmio_write_16(uintptr_t addr, uint16_t value) in mmio_write_16() argument
24 *(volatile uint16_t*)addr = value; in mmio_write_16()
39 static inline void mmio_write_32(uintptr_t addr, uint32_t value) in mmio_write_32() argument
41 *(volatile uint32_t*)addr = value; in mmio_write_32()
49 static inline void mmio_write_64(uintptr_t addr, uint64_t value) in mmio_write_64() argument
51 *(volatile uint64_t*)addr = value; in mmio_write_64()
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| H A D | utils_def.h | 140 #define round_boundary(value, boundary) \ argument
141 ((__typeof__(value))((boundary) - ((__typeof__(value))1U)))
143 #define round_up(value, boundary) \ argument
144 ((((value) - ((__typeof__(value))1U)) | round_boundary(value, boundary)) + ((__typeof__(value))1U))
146 #define round_down(value, boundary) \ argument
147 ((value) & ~round_boundary(value, boundary))
187 #define is_aligned(value, boundary) \ argument
188 (round_up((uintptr_t) value, boundary) == \
189 round_down((uintptr_t) value, boundary))
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/ |
| H A D | mt_spm_pmic_lp.c | 52 uint8_t value = VSRAM_CORE_0_55V; in get_vcore_sram_suspend_vol() local
66 value = vlp_vb_efuse_val_arr[volbin_efuse_reg]; in get_vcore_sram_suspend_vol()
69 value -= SUSPEND_AGING_VAL_SHIFT; in get_vcore_sram_suspend_vol()
70 if (value > SUSPEND_AGING_VAL_DEFAULT) in get_vcore_sram_suspend_vol()
71 value = SUSPEND_AGING_VAL_DEFAULT; in get_vcore_sram_suspend_vol()
73 value); in get_vcore_sram_suspend_vol()
77 value = SUSPEND_AGING_HV_VAL_DEFAULT; in get_vcore_sram_suspend_vol()
79 __LINE__, value); in get_vcore_sram_suspend_vol()
81 return value; in get_vcore_sram_suspend_vol()
191 uint8_t value = 0; in do_spm_low_power() local
[all …]
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| /rk3399_ARM-atf/plat/brcm/board/stingray/include/ |
| H A D | scp_utils.h | 22 #define SCP_WRITE_CFG(cfg, value) mmio_write_32(CRMU_CFG_BASE + \ argument
23 offsetof(M0CFG, cfg), value)
27 #define SCP_WRITE_CFG16(cfg, value) mmio_write_16(CRMU_CFG_BASE + \ argument
28 offsetof(M0CFG, cfg), value)
32 #define SCP_WRITE_CFG8(cfg, value) mmio_write_8(CRMU_CFG_BASE + \ argument
33 offsetof(M0CFG, cfg), value)
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| /rk3399_ARM-atf/drivers/arm/sp805/ |
| H A D | sp805.c | 14 static inline void sp805_write_wdog_load(uintptr_t base, uint32_t value) in sp805_write_wdog_load() argument
16 mmio_write_32(base + SP805_WDOG_LOAD_OFF, value); in sp805_write_wdog_load()
19 static inline void sp805_write_wdog_ctrl(uintptr_t base, uint32_t value) in sp805_write_wdog_ctrl() argument
21 mmio_write_32(base + SP805_WDOG_CTR_OFF, value); in sp805_write_wdog_ctrl()
24 static inline void sp805_write_wdog_lock(uintptr_t base, uint32_t value) in sp805_write_wdog_lock() argument
26 mmio_write_32(base + SP805_WDOG_LOCK_OFF, value); in sp805_write_wdog_lock()
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| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hikey_ddr.c | 1224 uint32_t value; in lpddrx_save_ddl_para_bypass() local
1229 value = mmio_read_32(0xf712c000 + 0x22c + i * 0x80); in lpddrx_save_ddl_para_bypass()
1230 ddr_ddl_para[cnt++] = value; in lpddrx_save_ddl_para_bypass()
1231 value = mmio_read_32(0xf712c000 + 0x23c + i * 0x80); in lpddrx_save_ddl_para_bypass()
1232 ddr_ddl_para[cnt++] = value; in lpddrx_save_ddl_para_bypass()
1233 value = mmio_read_32(0xf712c000 + 0x240 + i * 0x80); in lpddrx_save_ddl_para_bypass()
1234 ddr_ddl_para[cnt++] = value; in lpddrx_save_ddl_para_bypass()
1235 value = mmio_read_32(0xf712c000 + 0x640 + i * 0x80); in lpddrx_save_ddl_para_bypass()
1236 ddr_ddl_para[cnt++] = value; in lpddrx_save_ddl_para_bypass()
1242 uint32_t value; in lpddrx_save_ddl_para_mission() local
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/ |
| H A D | mt_spm_pmic_lp.c | 69 uint8_t value; in get_vcore_sram_suspend_vol() local
71 value = VSRAM_CORE_0_55V; in get_vcore_sram_suspend_vol()
74 value -= SUSPEND_AGING_VAL_SHIFT; in get_vcore_sram_suspend_vol()
75 if (value > SUSPEND_AGING_VAL_DEFAULT) in get_vcore_sram_suspend_vol()
76 value = SUSPEND_AGING_VAL_DEFAULT; in get_vcore_sram_suspend_vol()
78 __func__, __LINE__, value); in get_vcore_sram_suspend_vol()
80 return value; in get_vcore_sram_suspend_vol()
212 uint8_t value; in do_spm_low_power() local
220 value = vcore_sram_suspend_vol; in do_spm_low_power()
221 if (value < VSRAM_CORE_LOWBOUND || in do_spm_low_power()
[all …]
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| /rk3399_ARM-atf/drivers/st/bsec/ |
| H A D | bsec3.c | 197 bool value; in bsec_shadow_register() local
199 result = bsec_read_sr_lock(otp, &value); in bsec_shadow_register()
202 } else if (value) { in bsec_shadow_register()
265 bool value; in bsec_program_otp() local
275 result = bsec_read_sp_lock(otp, &value); in bsec_program_otp()
278 } else if (value) { in bsec_program_otp()
309 uint32_t value = mmio_read_32(BSEC_BASE + offset); in bsec_lock_register_set() local
312 if ((value & mask) != 0U) { in bsec_lock_register_set()
320 value |= mask; in bsec_lock_register_set()
322 mmio_write_32(BSEC_BASE + offset, value); in bsec_lock_register_set()
[all …]
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| /rk3399_ARM-atf/lib/compiler-rt/builtins/ |
| H A D | int_lib.h | 122 static int __inline __builtin_ctz(uint32_t value) { in __builtin_ctz() argument
124 if (_BitScanForward(&trailing_zero, value)) in __builtin_ctz()
129 static int __inline __builtin_clz(uint32_t value) { in __builtin_clz() argument
131 if (_BitScanReverse(&leading_zero, value)) in __builtin_clz()
137 static int __inline __builtin_clzll(uint64_t value) { in __builtin_clzll() argument
139 if (_BitScanReverse64(&leading_zero, value)) in __builtin_clzll()
144 static int __inline __builtin_clzll(uint64_t value) { in __builtin_clzll() argument
145 if (value == 0) in __builtin_clzll()
147 uint32_t msh = (uint32_t)(value >> 32); in __builtin_clzll()
148 uint32_t lsh = (uint32_t)(value & 0xFFFFFFFF); in __builtin_clzll()
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_ddr.c | 199 phys_size_t value; in sdram_set_firewall_non_f2sdram() local
207 value = ddr_info_set[i].start; in sdram_set_firewall_non_f2sdram()
213 value += SZ_1M; in sdram_set_firewall_non_f2sdram()
216 lower = LO(value); in sdram_set_firewall_non_f2sdram()
217 upper = HI(value); in sdram_set_firewall_non_f2sdram()
235 value = ddr_info_set[i].start + ddr_info_set[i].size - 1; in sdram_set_firewall_non_f2sdram()
237 lower = LO(value); in sdram_set_firewall_non_f2sdram()
238 upper = HI(value); in sdram_set_firewall_non_f2sdram()
263 phys_size_t value; in sdram_set_firewall_f2sdram() local
271 value = ddr_info_set[i].start; in sdram_set_firewall_f2sdram()
[all …]
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| /rk3399_ARM-atf/docs/components/ |
| H A D | ffa-manifest-binding.rst | 14 - value type: <string>
24 - value type: <u32>
34 - value type: <prop-encoded-array>
44 - value type: <u32>
48 - value type: <u32>
52 - value type: <string>
56 - value type: <u32>
61 - If value of this field = 1 and number of PEs > 1 then the partition is
63 - If the value of this field > 1 then the partition is treated as a MP
67 - value type: <u32>
[all …]
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| /rk3399_ARM-atf/drivers/cadence/emmc/ |
| H A D | cdns_sdmmc.c | 114 uint32_t value = 0; in cdns_program_phy_reg() local
133 value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09); in cdns_program_phy_reg()
134 value &= ~SDHC_PHY_SW_RESET; in cdns_program_phy_reg()
135 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09, value); in cdns_program_phy_reg()
138 value = (CP_USE_EXT_LPBK_DQS(combo_phy_reg->cp_use_ext_lpbk_dqs)) | in cdns_program_phy_reg()
144 cdns_params.reg_base + SDHC_CDNS_HRS05, value); in cdns_program_phy_reg()
150 value = (CP_SYNC_METHOD(combo_phy_reg->cp_sync_method)) | in cdns_program_phy_reg()
157 cdns_params.reg_base + SDHC_CDNS_HRS05, value); in cdns_program_phy_reg()
163 value = (CP_DLL_BYPASS_MODE(combo_phy_reg->cp_dll_bypass_mode)) | (2 << 20) | in cdns_program_phy_reg()
167 cdns_params.reg_base + SDHC_CDNS_HRS05, value); in cdns_program_phy_reg()
[all …]
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| /rk3399_ARM-atf/common/ |
| H A D | fdt_wrappers.c | 27 unsigned int cells, uint32_t *value) in fdt_read_uint32_array() argument
34 assert(value != NULL); in fdt_read_uint32_array()
51 value[i] = fdt32_to_cpu(prop[i]); in fdt_read_uint32_array()
58 uint32_t *value) in fdt_read_uint32() argument
60 return fdt_read_uint32_array(dtb, node, prop_name, 1, value); in fdt_read_uint32()
77 uint64_t *value) in fdt_read_uint64() argument
87 *value = ((uint64_t)array[0] << 32) | array[1]; in fdt_read_uint64()
110 unsigned int length, void *value) in fdtw_read_bytes() argument
117 assert(value != NULL); in fdtw_read_bytes()
134 (void)memcpy(value, ptr, length); in fdtw_read_bytes()
[all …]
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| /rk3399_ARM-atf/drivers/arm/sbsa/ |
| H A D | sbsa.c | 13 void sbsa_watchdog_offset_reg_write(uintptr_t base, uint64_t value) in sbsa_watchdog_offset_reg_write() argument
15 assert((value >> SBSA_WDOG_WOR_WIDTH) == 0); in sbsa_watchdog_offset_reg_write()
17 ((uint32_t)value & UINT32_MAX)); in sbsa_watchdog_offset_reg_write()
18 mmio_write_32(base + SBSA_WDOG_WOR_HIGH_OFFSET, (uint32_t)(value >> 32)); in sbsa_watchdog_offset_reg_write()
|