1 /*
2 * Copyright (c) 2025, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch.h>
8 #include <arch_features.h>
9 #include <arch_helpers.h>
10 #include <context.h>
11 #include <lib/el3_runtime/context_mgmt.h>
12 #include <lib/el3_runtime/cpu_data.h>
13 #include <lib/extensions/idte3.h>
14
idte3_init_percpu_once_regs(size_t security_state)15 void idte3_init_percpu_once_regs(size_t security_state)
16 {
17 assert(security_state < CPU_CONTEXT_NUM);
18
19 percpu_idregs_t * const reg =
20 &get_cpu_data(idregs[security_state]);
21
22 reg->id_aa64dfr0_el1 = read_id_aa64dfr0_el1();
23 reg->id_aa64dfr1_el1 = read_id_aa64dfr1_el1();
24
25 update_feat_spe_idreg_field(security_state);
26 update_feat_brbe_idreg_field(security_state);
27 update_feat_trbe_idreg_field(security_state);
28 update_feat_trf_idreg_field(security_state);
29 update_feat_mtpmu_idreg_field(security_state);
30 update_feat_sebep_idreg_field(security_state);
31 update_feat_sys_reg_trace_idreg_field(security_state);
32 update_feat_debugv8p9_idreg_field(security_state);
33 update_feat_ebep_idreg_field(security_state);
34 }
35
idte3_init_cached_idregs_per_world(size_t security_state)36 void idte3_init_cached_idregs_per_world(size_t security_state)
37 {
38
39 assert(security_state < CPU_CONTEXT_NUM);
40
41 per_world_context_t *per_world_ctx = &per_world_context[security_state];
42 perworld_idregs_t *reg = &(per_world_ctx->idregs);
43
44 reg->id_aa64pfr0_el1 = read_id_aa64pfr0_el1();
45 reg->id_aa64pfr1_el1 = read_id_aa64pfr1_el1();
46 reg->id_aa64pfr2_el1 = read_id_aa64pfr2_el1();
47 reg->id_aa64smfr0_el1 = read_id_aa64smfr0_el1();
48 reg->id_aa64isar0_el1 = read_id_aa64isar0_el1();
49 reg->id_aa64isar1_el1 = read_id_aa64isar1_el1();
50 reg->id_aa64isar2_el1 = read_id_aa64isar2_el1();
51 reg->id_aa64isar3_el1 = read_id_aa64isar3_el1();
52 reg->id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1();
53 reg->id_aa64mmfr1_el1 = read_id_aa64mmfr1_el1();
54 reg->id_aa64mmfr2_el1 = read_id_aa64mmfr2_el1();
55 reg->id_aa64mmfr3_el1 = read_id_aa64mmfr3_el1();
56 reg->id_aa64mmfr4_el1 = read_id_aa64mmfr4_el1();
57
58 update_feat_pan_idreg_field(security_state);
59 update_feat_vhe_idreg_field(security_state);
60 update_feat_ttcnp_idreg_field(security_state);
61 update_feat_uao_idreg_field(security_state);
62 update_feat_pacqarma3_idreg_field(security_state);
63 update_feat_pauth_idreg_field(security_state);
64 update_feat_ttst_idreg_field(security_state);
65 update_feat_bti_idreg_field(security_state);
66 update_feat_mte2_idreg_field(security_state);
67 update_feat_ssbs_idreg_field(security_state);
68 update_feat_nmi_idreg_field(security_state);
69 update_feat_gcs_idreg_field(security_state);
70 update_feat_ebep_idreg_field(security_state);
71 update_feat_sel2_idreg_field(security_state);
72 update_feat_twed_idreg_field(security_state);
73 update_feat_fgt_idreg_field(security_state);
74 update_feat_ecv_idreg_field(security_state);
75 update_feat_rng_idreg_field(security_state);
76 update_feat_tcr2_idreg_field(security_state);
77 update_feat_s2poe_idreg_field(security_state);
78 update_feat_s1poe_idreg_field(security_state);
79 update_feat_s2pie_idreg_field(security_state);
80 update_feat_s1pie_idreg_field(security_state);
81 update_feat_amu_idreg_field(security_state);
82 update_feat_mpam_idreg_field(security_state);
83 update_feat_hcx_idreg_field(security_state);
84 update_feat_rng_trap_idreg_field(security_state);
85 update_feat_sb_idreg_field(security_state);
86 update_feat_csv2_2_idreg_field(security_state);
87 update_feat_sve_idreg_field(security_state);
88 update_feat_ras_idreg_field(security_state);
89 update_feat_dit_idreg_field(security_state);
90 update_feat_trbe_idreg_field(security_state);
91 update_feat_sme_idreg_field(security_state);
92 update_feat_fgt2_idreg_field(security_state);
93 update_feat_the_idreg_field(security_state);
94 update_feat_sctlr2_idreg_field(security_state);
95 update_feat_d128_idreg_field(security_state);
96 update_feat_ls64_accdata_idreg_field(security_state);
97 update_feat_fpmr_idreg_field(security_state);
98 update_feat_mops_idreg_field(security_state);
99 update_feat_fgwte3_idreg_field(security_state);
100 update_feat_cpa2_idreg_field(security_state);
101 update_feat_idte3_idreg_field(security_state);
102 }
103
handle_idreg_trap(uint64_t esr_el3,cpu_context_t * ctx,u_register_t flags)104 int handle_idreg_trap(uint64_t esr_el3, cpu_context_t *ctx, u_register_t flags)
105 {
106 uint32_t iss = (uint32_t) ESR_ELx_ISS(esr_el3);
107 uint8_t rt = (uint8_t) ISS_SYS64_RT(iss);
108 uint8_t op0 = (uint8_t) ISS_SYS64_OP0(iss);
109 uint8_t op1 = (uint8_t) ISS_SYS64_OP1(iss);
110 uint8_t CRn = (uint8_t) ISS_SYS64_CRN(iss);
111 uint8_t CRm = (uint8_t) ISS_SYS64_CRM(iss);
112 uint8_t op2 = (uint8_t) ISS_SYS64_OP2(iss);
113
114 u_register_t idreg = esr_el3 & ESR_EL3_SYSREG_MASK;
115
116 u_register_t value = 0ULL;
117 size_t security_state = GET_SECURITY_STATE(flags);
118 percpu_idregs_t *percpu_reg = &(get_cpu_data(idregs[security_state]));
119
120 per_world_context_t *per_world_ctx =
121 &per_world_context[get_cpu_context_index(security_state)];
122 perworld_idregs_t *perworld_reg = &(per_world_ctx->idregs);
123
124 switch (idreg) {
125 case ESR_EL3_IDREG_ID_AA64PFR0_EL1:
126 value = perworld_reg->id_aa64pfr0_el1;
127 break;
128 case ESR_EL3_IDREG_ID_AA64PFR1_EL1:
129 value = perworld_reg->id_aa64pfr1_el1;
130 break;
131 case ESR_EL3_IDREG_ID_AA64PFR2_EL1:
132 value = perworld_reg->id_aa64pfr2_el1;
133 break;
134 case ESR_EL3_IDREG_ID_AA64SMFR0_EL1:
135 value = perworld_reg->id_aa64smfr0_el1;
136 break;
137 case ESR_EL3_IDREG_ID_AA64ISAR0_EL1:
138 value = perworld_reg->id_aa64isar0_el1;
139 break;
140 case ESR_EL3_IDREG_ID_AA64ISAR1_EL1:
141 value = perworld_reg->id_aa64isar1_el1;
142 break;
143 case ESR_EL3_IDREG_ID_AA64ISAR2_EL1:
144 value = perworld_reg->id_aa64isar2_el1;
145 break;
146 case ESR_EL3_IDREG_ID_AA64ISAR3_EL1:
147 value = perworld_reg->id_aa64isar3_el1;
148 break;
149 case ESR_EL3_IDREG_ID_AA64MMFR0_EL1:
150 value = perworld_reg->id_aa64mmfr0_el1;
151 break;
152 case ESR_EL3_IDREG_ID_AA64MMFR1_EL1:
153 value = perworld_reg->id_aa64mmfr1_el1;
154 break;
155 case ESR_EL3_IDREG_ID_AA64MMFR2_EL1:
156 value = perworld_reg->id_aa64mmfr2_el1;
157 break;
158 case ESR_EL3_IDREG_ID_AA64MMFR3_EL1:
159 value = perworld_reg->id_aa64mmfr3_el1;
160 break;
161 case ESR_EL3_IDREG_ID_AA64MMFR4_EL1:
162 value = perworld_reg->id_aa64mmfr4_el1;
163 break;
164 case ESR_EL3_IDREG_ID_AA64DFR0_EL1:
165 value = percpu_reg->id_aa64dfr0_el1;
166 break;
167 case ESR_EL3_IDREG_ID_AA64DFR1_EL1:
168 value = percpu_reg->id_aa64dfr1_el1;
169 break;
170 case ESR_EL3_IDREG_ID_AA64ZFR0_EL1:
171 value = read_id_aa64zfr0_el1();
172 break;
173 case ESR_EL3_IDREG_ID_AA64FPFR0_EL1:
174 value = read_id_aa64fpfr0_el1();
175 break;
176 case ESR_EL3_IDREG_ID_AA64DFR2_EL1:
177 value = read_id_aa64dfr2_el1();
178 break;
179 case ESR_EL3_IDREG_ID_AA64AFR0_EL1:
180 value = read_id_aa64afr0_el1();
181 break;
182 case ESR_EL3_IDREG_ID_AA64AFR1_EL1:
183 value = read_id_aa64afr1_el1();
184 break;
185 case ESR_EL3_IDREG_GMID_EL1:
186 value = read_gmid_el1();
187 break;
188 case ESR_EL3_IDREG_ID_PFR0_EL1:
189 value = read_id_pfr0_el1();
190 break;
191 case ESR_EL3_IDREG_ID_PFR1_EL1:
192 value = read_id_pfr1_el1();
193 break;
194 case ESR_EL3_IDREG_ID_DFR0_EL1:
195 value = read_id_dfr0_el1();
196 break;
197 case ESR_EL3_IDREG_ID_AFR0_EL1:
198 value = read_id_afr0_el1();
199 break;
200 case ESR_EL3_IDREG_ID_PFR2_EL1:
201 value = read_id_pfr2_el1();
202 break;
203 case ESR_EL3_IDREG_ID_DFR1_EL1:
204 value = read_id_dfr1_el1();
205 break;
206 case ESR_EL3_IDREG_ID_MMFR0_EL1:
207 value = read_id_mmfr0_el1();
208 break;
209 case ESR_EL3_IDREG_ID_MMFR1_EL1:
210 value = read_id_mmfr1_el1();
211 break;
212 case ESR_EL3_IDREG_ID_MMFR2_EL1:
213 value = read_id_mmfr2_el1();
214 break;
215 case ESR_EL3_IDREG_ID_MMFR3_EL1:
216 value = read_id_mmfr3_el1();
217 break;
218 case ESR_EL3_IDREG_ID_MMFR4_EL1:
219 value = read_id_mmfr4_el1();
220 break;
221 case ESR_EL3_IDREG_ID_MMFR5_EL1:
222 value = read_id_mmfr5_el1();
223 break;
224 case ESR_EL3_IDREG_ID_ISAR0_EL1:
225 value = read_id_isar0_el1();
226 break;
227 case ESR_EL3_IDREG_ID_ISAR1_EL1:
228 value = read_id_isar1_el1();
229 break;
230 case ESR_EL3_IDREG_ID_ISAR2_EL1:
231 value = read_id_isar2_el1();
232 break;
233 case ESR_EL3_IDREG_ID_ISAR3_EL1:
234 value = read_id_isar3_el1();
235 break;
236 case ESR_EL3_IDREG_ID_ISAR4_EL1:
237 value = read_id_isar4_el1();
238 break;
239 case ESR_EL3_IDREG_ID_ISAR5_EL1:
240 value = read_id_isar5_el1();
241 break;
242 case ESR_EL3_IDREG_ID_ISAR6_EL1:
243 value = read_id_isar6_el1();
244 break;
245 case ESR_EL3_IDREG_MVFR0_EL1:
246 value = read_mvfr0_el1();
247 break;
248 case ESR_EL3_IDREG_MVFR1_EL1:
249 value = read_mvfr1_el1();
250 break;
251 case ESR_EL3_IDREG_MVFR2_EL1:
252 value = read_mvfr2_el1();
253 break;
254
255 /*
256 * Any ID register access that falls within the Group 3
257 * ID space (op0 == 3, op1 == 0, CRn == 0, CRm == {2-7}, op2 == {0-7})
258 * but is not explicitly handled here will return 0.
259 * This covers newly introduced ID registers that were previously
260 * reserved or unknown.
261 *
262 * When new ID registers are added in future revisions of
263 * the architecture, they must be explicitly handled in this
264 * switch statement to return their actual value instead of
265 * Res0.
266 */
267 default:
268 WARN("Unknown ID register: S%u_%u_C%u_C%u_%u is trapped\n",
269 op0, op1, CRn, CRm, op2);
270 value = 0UL;
271 }
272
273 ctx->gpregs_ctx.ctx_regs[rt] = value;
274 return TRAP_RET_CONTINUE;
275 }
276
idte3_enable(cpu_context_t * context)277 void idte3_enable(cpu_context_t *context)
278 {
279 u_register_t reg;
280 el3_state_t *state;
281
282 state = get_el3state_ctx(context);
283
284 /*
285 * Setting the TID3 & TID5 bits enables trapping for
286 * group 3 ID registers and group 5
287 * ID register - GMID_EL1.
288 */
289
290 reg = read_ctx_reg(state, CTX_SCR_EL3);
291 reg |= (SCR_TID3_BIT | SCR_TID5_BIT);
292 write_ctx_reg(state, CTX_SCR_EL3, reg);
293 }
294