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Searched refs:regs (Results 1 – 25 of 35) sorted by relevance

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/rk3399_ARM-atf/drivers/nxp/ddr/phy-gen1/
H A Dphy.c17 static void cal_ddr_sdram_clk_cntl(struct ddr_cfg_regs *regs, in cal_ddr_sdram_clk_cntl() argument
23 regs->clk_cntl = ((ss_en & U(0x1)) << 31U) | in cal_ddr_sdram_clk_cntl()
25 debug("clk_cntl = 0x%x\n", regs->clk_cntl); in cal_ddr_sdram_clk_cntl()
28 static void cal_ddr_cdr(struct ddr_cfg_regs *regs, in cal_ddr_cdr() argument
31 regs->cdr[0] = popts->ddr_cdr1; in cal_ddr_cdr()
32 regs->cdr[1] = popts->ddr_cdr2; in cal_ddr_cdr()
33 debug("cdr[0] = 0x%x\n", regs->cdr[0]); in cal_ddr_cdr()
34 debug("cdr[1] = 0x%x\n", regs->cdr[1]); in cal_ddr_cdr()
37 static void cal_ddr_wrlvl_cntl(struct ddr_cfg_regs *regs, in cal_ddr_wrlvl_cntl() argument
49 regs->wrlvl_cntl[0] = ((wrlvl_en & U(0x1)) << 31U) | in cal_ddr_wrlvl_cntl()
[all …]
/rk3399_ARM-atf/drivers/nxp/ddr/nxp-ddr/
H A Dddrc.c189 const struct ddr_cfg_regs *regs, in ddrc_set_regs() argument
196 const int mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK; in ddrc_set_regs()
214 ddr_out32(&ddr->ddr_cdr1, regs->cdr[0]); in ddrc_set_regs()
216 ddr_out32(&ddr->sdram_clk_cntl, regs->clk_cntl); in ddrc_set_regs()
221 (regs->cs[i].bnds & U(0xfffefffe)) >> 1U); in ddrc_set_regs()
223 ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds); in ddrc_set_regs()
225 ddr_out32(&ddr->csn_cfg_2[i], regs->cs[i].config_2); in ddrc_set_regs()
228 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg[0]); in ddrc_set_regs()
229 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg[1]); in ddrc_set_regs()
230 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg[2]); in ddrc_set_regs()
[all …]
H A Dregs.c31 struct ddr_cfg_regs *regs, in cal_csn_config() argument
59 regs->cs[i].config = ((cs_n_en & 0x1) << 31) | in cal_csn_config()
70 debug(" _config = 0x%x\n", regs->cs[i].config); in cal_csn_config()
90 struct ddr_cfg_regs *regs, in cal_timing_cfg() argument
228 regs->timing_cfg[0] = (((trwt_mclk & 0x3) << 30) | in cal_timing_cfg()
236 debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]); in cal_timing_cfg()
253 regs->timing_cfg[1] = (((pretoact_mclk & 0x0F) << 28) | in cal_timing_cfg()
261 debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]); in cal_timing_cfg()
270 regs->timing_cfg[2] = (((additive_latency & 0xf) << 28) | in cal_timing_cfg()
278 debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]); in cal_timing_cfg()
[all …]
/rk3399_ARM-atf/lib/el3_runtime/
H A Dsimd_ctx.c32 simd_regs_t *regs; in simd_ctx_save() local
40 regs = &simd_context[security_state][plat_my_core_pos()]; in simd_ctx_save()
43 regs->hint = hint_sve; in simd_ctx_save()
50 fpregs_context_save(regs); in simd_ctx_save()
52 sve_context_save(regs); in simd_ctx_save()
55 fpregs_context_save(regs); in simd_ctx_save()
61 simd_regs_t *regs; in simd_ctx_restore() local
69 regs = &simd_context[security_state][plat_my_core_pos()]; in simd_ctx_restore()
72 if (regs->hint) { in simd_ctx_restore()
73 fpregs_context_restore(regs); in simd_ctx_restore()
[all …]
/rk3399_ARM-atf/drivers/nxp/crypto/caam/src/
H A Dsec_hw_specific.c32 static inline void hw_set_input_ring_start_addr(struct jobring_regs *regs, in hw_set_input_ring_start_addr() argument
36 sec_out32(&regs->irba_h, PHYS_ADDR_HI(start_addr)); in hw_set_input_ring_start_addr()
38 sec_out32(&regs->irba_h, 0); in hw_set_input_ring_start_addr()
40 sec_out32(&regs->irba_l, PHYS_ADDR_LO(start_addr)); in hw_set_input_ring_start_addr()
43 static inline void hw_set_output_ring_start_addr(struct jobring_regs *regs, in hw_set_output_ring_start_addr() argument
47 sec_out32(&regs->orba_h, PHYS_ADDR_HI(start_addr)); in hw_set_output_ring_start_addr()
49 sec_out32(&regs->orba_h, 0); in hw_set_output_ring_start_addr()
51 sec_out32(&regs->orba_l, PHYS_ADDR_LO(start_addr)); in hw_set_output_ring_start_addr()
60 struct jobring_regs *regs = in hw_remove_entries() local
63 sec_out32(&regs->orjr, num); in hw_remove_entries()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/pmic/
H A Dpmic_psc.c28 reg = &pmic_psc->regs[reg_name]; in read_pmic_psc_reg()
40 reg = &pmic_psc->regs[reg_name]; in set_pmic_psc_reg()
52 reg = &pmic_psc->regs[reg_name]; in clr_pmic_psc_reg()
84 if (!pmic_psc->regs[RG_CRST].reg_addr) in platform_cold_reset()
112 if (!psc || !psc->regs || !psc->read_field || !psc->write_field) in pmic_psc_register()
/rk3399_ARM-atf/plat/mediatek/drivers/spmi/
H A Dpmif_common.c62 offset = arb->regs[PMIF_SWINF_3_STA]; in pmif_check_idle()
75 offset = arb->regs[PMIF_SWINF_3_STA]; in pmif_check_vldclr()
110 offset = arb->regs[PMIF_SWINF_3_ACC]; in pmif_spmi_read_cmd()
120 offset = arb->regs[PMIF_SWINF_3_RDATA_31_0]; in pmif_spmi_read_cmd()
125 offset = arb->regs[PMIF_SWINF_3_VLD_CLR]; in pmif_spmi_read_cmd()
163 offset = arb->regs[PMIF_SWINF_3_WDATA_31_0]; in pmif_spmi_write_cmd()
167 offset = arb->regs[PMIF_SWINF_3_ACC]; in pmif_spmi_write_cmd()
H A Dpmif_common.h21 uint16_t *regs; member
/rk3399_ARM-atf/include/lib/extensions/
H A Dsve.h34 void sve_context_save(simd_regs_t *regs);
35 void sve_context_restore(simd_regs_t *regs);
/rk3399_ARM-atf/plat/marvell/armada/a8k/common/mss/
H A Dmss_bl31_setup.c22 uintptr_t regs = MVEBU_CP_REGS_BASE(cp) + MSS_CP_REGS_OFFSET; in mss_start_cp_cm3() local
35 mmio_write_32(MSS_M3_RSTCR(regs), in mss_start_cp_cm3()
/rk3399_ARM-atf/plat/imx/imx9/common/
H A Dimx9_sys_sleep.c103 wdog->regs[0] = mmio_read_32(wdog->base); in wdog_save()
104 wdog->regs[1] = mmio_read_32(wdog->base + 0x8); in wdog_save()
115 if (cs == wdog->regs[0] && toval == wdog->regs[1]) { in wdog_restore()
120 mmio_write_32(wdog->base, wdog->regs[0]); in wdog_restore()
122 mmio_write_32(wdog->base + 0x8, wdog->regs[1]); in wdog_restore()
/rk3399_ARM-atf/plat/mediatek/drivers/spmi/mt8189/
H A Dplatform_pmif_spmi.c97 .regs = mt6xxx_regs,
104 .regs = mt6xxx_regs,
112 .regs = mt6xxx_regs,
/rk3399_ARM-atf/include/arch/aarch64/
H A Dsmccc_helpers.h110 const gp_regs_t *regs = get_gpregs_ctx(_hdl); \
111 _x1 = read_ctx_reg(regs, CTX_GPREG_X1); \
112 _x2 = read_ctx_reg(regs, CTX_GPREG_X2); \
113 _x3 = read_ctx_reg(regs, CTX_GPREG_X3); \
114 _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \
/rk3399_ARM-atf/plat/arm/board/common/
H A Dboard_common.mk19 ifeq (${ARM_ROTPK_LOCATION}, regs)
29 $(warning Development keys support for FVP is deprecated. Use `regs` \
35 $(warning Development keys support for FVP is deprecated. Use `regs` \
42 $(warning Development keys support for FVP is deprecated. Use `regs` \
49 $(warning Development keys support for FVP is deprecated. Use `regs` \
/rk3399_ARM-atf/drivers/nxp/ddr/phy-gen2/
H A Dphy.c2488 struct ddr_cfg_regs *regs = &priv->ddr_reg; in compute_ddr_phy() local
2532 input.mr[0] = regs->sdram_mode[0] & U(0xffff); in compute_ddr_phy()
2533 input.mr[1] = regs->sdram_mode[0] >> 16U; in compute_ddr_phy()
2534 input.mr[2] = regs->sdram_mode[1] >> 16U; in compute_ddr_phy()
2535 input.mr[3] = regs->sdram_mode[1] & U(0xffff); in compute_ddr_phy()
2536 input.mr[4] = regs->sdram_mode[8] >> 16U; in compute_ddr_phy()
2537 input.mr[5] = regs->sdram_mode[8] & U(0xffff); in compute_ddr_phy()
2538 input.mr[6] = regs->sdram_mode[9] >> 16U; in compute_ddr_phy()
2542 if ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) == 0U) { in compute_ddr_phy()
2545 odt_rd = (regs->cs[i].config >> 20U) & U(0x7); in compute_ddr_phy()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/pmic/mt6359p/
H A Dmt6359p_psc.c25 .regs = mt6359p_psc_regs,
/rk3399_ARM-atf/plat/mediatek/drivers/spmi/mt8196/
H A Dplatform_pmif_spmi.c108 .regs = mt6xxx_regs,
116 .regs = mt6xxx_regs,
124 .regs = mt6xxx_regs,
/rk3399_ARM-atf/plat/mediatek/include/drivers/pmic/
H A Dpmic_psc.h28 const struct pmic_psc_reg *regs; member
/rk3399_ARM-atf/include/services/trp/
H A Dtrp_helpers.h32 uint64_t regs[TRP_ARGS_END >> 3]; member
/rk3399_ARM-atf/plat/imx/imx9/common/include/
H A Dimx9_sys_sleep.h38 uint32_t regs[2]; member
/rk3399_ARM-atf/services/std_svc/rmmd/trp/
H A Dtrp_private.h25 #define write_trp_arg(args, offset, val) (((args)->regs[offset >> 3]) \
/rk3399_ARM-atf/include/lib/el3_runtime/aarch32/
H A Dcontext.h46 DEFINE_REG_STRUCT(regs, CTX_REG_ALL);
/rk3399_ARM-atf/plat/mediatek/drivers/pmic/mt6363/
H A Dmt6363_psc.c65 .regs = mt6363_psc_regs,
/rk3399_ARM-atf/include/drivers/nxp/ddr/
H A Dddr.h136 const struct ddr_cfg_regs *regs,
/rk3399_ARM-atf/plat/nxp/soc-ls1046a/ls1046ardb/
H A Dddr_init.c160 const struct ddr_cfg_regs *regs; member
182 memcpy(&priv->ddr_reg, table[i].regs, in board_static_ddr()

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