xref: /rk3399_ARM-atf/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c (revision 52c47c174fadb9e1398af41e9bbf290af314e8ec)
1*868b2d60SZhigang Qin /*
2*868b2d60SZhigang Qin  * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3*868b2d60SZhigang Qin  * SPDX-License-Identifier: BSD-3-Clause
4*868b2d60SZhigang Qin  */
5*868b2d60SZhigang Qin 
6*868b2d60SZhigang Qin #include <errno.h>
7*868b2d60SZhigang Qin 
8*868b2d60SZhigang Qin #include <common/debug.h>
9*868b2d60SZhigang Qin #include <drivers/pmic/pmic_psc.h>
10*868b2d60SZhigang Qin #include <lib/mtk_init/mtk_init.h>
11*868b2d60SZhigang Qin #include <pmic_wrap_init_common.h>
12*868b2d60SZhigang Qin 
13*868b2d60SZhigang Qin #include "registers.h"
14*868b2d60SZhigang Qin 
15*868b2d60SZhigang Qin static const struct pmic_psc_reg mt6359p_psc_regs[] = {
16*868b2d60SZhigang Qin 	PMIC_PSC_REG(RG_PWRHOLD, MT6359P_PPCCTL0, 0),
17*868b2d60SZhigang Qin 	PMIC_PSC_REG(RG_CRST, MT6359P_PPCCTL1, 0),
18*868b2d60SZhigang Qin 	PMIC_PSC_REG(RG_SMART_RST_SDN_EN, MT6359P_STRUP_CON12, 9),
19*868b2d60SZhigang Qin 	PMIC_PSC_REG(RG_SMART_RST_MODE, MT6359P_STRUP_CON12, 10),
20*868b2d60SZhigang Qin };
21*868b2d60SZhigang Qin 
22*868b2d60SZhigang Qin static const struct pmic_psc_config mt6359p_psc_config = {
23*868b2d60SZhigang Qin 	.read_field = pwrap_read_field,
24*868b2d60SZhigang Qin 	.write_field = pwrap_write_field,
25*868b2d60SZhigang Qin 	.regs = mt6359p_psc_regs,
26*868b2d60SZhigang Qin 	.reg_size = ARRAY_SIZE(mt6359p_psc_regs),
27*868b2d60SZhigang Qin };
28*868b2d60SZhigang Qin 
mt6359p_psc_init(void)29*868b2d60SZhigang Qin static int mt6359p_psc_init(void)
30*868b2d60SZhigang Qin {
31*868b2d60SZhigang Qin 	return pmic_psc_register(&mt6359p_psc_config);
32*868b2d60SZhigang Qin }
33*868b2d60SZhigang Qin 
34*868b2d60SZhigang Qin MTK_PLAT_SETUP_0_INIT(mt6359p_psc_init);
35