1*d4e6f98dSHope Wang /* 2*d4e6f98dSHope Wang * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3*d4e6f98dSHope Wang * 4*d4e6f98dSHope Wang * SPDX-License-Identifier: BSD-3-Clause 5*d4e6f98dSHope Wang */ 6*d4e6f98dSHope Wang 7*d4e6f98dSHope Wang #ifndef PMIC_PSC_H 8*d4e6f98dSHope Wang #define PMIC_PSC_H 9*d4e6f98dSHope Wang 10*d4e6f98dSHope Wang #include <stdint.h> 11*d4e6f98dSHope Wang 12*d4e6f98dSHope Wang enum pmic_psc_reg_name { 13*d4e6f98dSHope Wang RG_PWRHOLD, 14*d4e6f98dSHope Wang RG_CRST, 15*d4e6f98dSHope Wang RG_SMART_RST_SDN_EN, 16*d4e6f98dSHope Wang RG_SMART_RST_MODE, 17*d4e6f98dSHope Wang }; 18*d4e6f98dSHope Wang 19*d4e6f98dSHope Wang struct pmic_psc_reg { 20*d4e6f98dSHope Wang uint16_t reg_addr; 21*d4e6f98dSHope Wang uint16_t reg_mask; 22*d4e6f98dSHope Wang uint16_t reg_shift; 23*d4e6f98dSHope Wang }; 24*d4e6f98dSHope Wang 25*d4e6f98dSHope Wang struct pmic_psc_config { 26*d4e6f98dSHope Wang int (*read_field)(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift); 27*d4e6f98dSHope Wang int (*write_field)(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift); 28*d4e6f98dSHope Wang const struct pmic_psc_reg *regs; 29*d4e6f98dSHope Wang const uint32_t reg_size; 30*d4e6f98dSHope Wang }; 31*d4e6f98dSHope Wang 32*d4e6f98dSHope Wang #define PMIC_PSC_REG(_reg_name, addr, shift) \ 33*d4e6f98dSHope Wang [_reg_name] = { \ 34*d4e6f98dSHope Wang .reg_addr = addr, \ 35*d4e6f98dSHope Wang .reg_mask = 0x1, \ 36*d4e6f98dSHope Wang .reg_shift = shift, \ 37*d4e6f98dSHope Wang } 38*d4e6f98dSHope Wang 39*d4e6f98dSHope Wang int enable_pmic_smart_reset(bool enable); 40*d4e6f98dSHope Wang int enable_pmic_smart_reset_shutdown(bool enable); 41*d4e6f98dSHope Wang int platform_cold_reset(void); 42*d4e6f98dSHope Wang int platform_power_hold(bool hold); 43*d4e6f98dSHope Wang int pmic_psc_register(const struct pmic_psc_config *psc); 44*d4e6f98dSHope Wang 45*d4e6f98dSHope Wang #endif /* PMIC_PSC_H */ 46