1*b5a06637SKonstantin Porotchkin /* 2*b5a06637SKonstantin Porotchkin * Copyright (C) 2021 Marvell International Ltd. 3*b5a06637SKonstantin Porotchkin * 4*b5a06637SKonstantin Porotchkin * SPDX-License-Identifier: BSD-3-Clause 5*b5a06637SKonstantin Porotchkin * https://spdx.org/licenses 6*b5a06637SKonstantin Porotchkin */ 7*b5a06637SKonstantin Porotchkin 8*b5a06637SKonstantin Porotchkin #include <platform_def.h> 9*b5a06637SKonstantin Porotchkin 10*b5a06637SKonstantin Porotchkin #include <common/bl_common.h> 11*b5a06637SKonstantin Porotchkin #include <common/debug.h> 12*b5a06637SKonstantin Porotchkin #include <lib/mmio.h> 13*b5a06637SKonstantin Porotchkin 14*b5a06637SKonstantin Porotchkin #include <armada_common.h> 15*b5a06637SKonstantin Porotchkin 16*b5a06637SKonstantin Porotchkin #include "mss_defs.h" 17*b5a06637SKonstantin Porotchkin mss_start_cp_cm3(int cp)18*b5a06637SKonstantin Porotchkinvoid mss_start_cp_cm3(int cp) 19*b5a06637SKonstantin Porotchkin { 20*b5a06637SKonstantin Porotchkin uint32_t magic; 21*b5a06637SKonstantin Porotchkin uintptr_t sram = MVEBU_CP_REGS_BASE(cp) + MSS_CP_SRAM_OFFSET; 22*b5a06637SKonstantin Porotchkin uintptr_t regs = MVEBU_CP_REGS_BASE(cp) + MSS_CP_REGS_OFFSET; 23*b5a06637SKonstantin Porotchkin 24*b5a06637SKonstantin Porotchkin magic = mmio_read_32(sram); 25*b5a06637SKonstantin Porotchkin 26*b5a06637SKonstantin Porotchkin /* Make sure the FW was loaded */ 27*b5a06637SKonstantin Porotchkin if (magic != MSS_FW_READY_MAGIC) { 28*b5a06637SKonstantin Porotchkin return; 29*b5a06637SKonstantin Porotchkin } 30*b5a06637SKonstantin Porotchkin 31*b5a06637SKonstantin Porotchkin NOTICE("Starting CP%d MSS CPU\n", cp); 32*b5a06637SKonstantin Porotchkin /* remove the magic */ 33*b5a06637SKonstantin Porotchkin mmio_write_32(sram, 0); 34*b5a06637SKonstantin Porotchkin /* Release M3 from reset */ 35*b5a06637SKonstantin Porotchkin mmio_write_32(MSS_M3_RSTCR(regs), 36*b5a06637SKonstantin Porotchkin (MSS_M3_RSTCR_RST_OFF << MSS_M3_RSTCR_RST_OFFSET)); 37*b5a06637SKonstantin Porotchkin } 38