| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/ |
| H A D | apupll.c | 127 static const char *pllidx2name(int32_t pll_idx) in pllidx2name() argument
137 if (pll_idx >= APUPLL_MAX) { in pllidx2name()
138 pll_idx = APUPLL_MAX; in pllidx2name()
141 return names[pll_idx]; in pllidx2name()
157 static int32_t _fhctl_mon_done(uint32_t pll_idx, unsigned long tar_dds) in _fhctl_mon_done() argument
165 mon_dds = apupwr_readl(fhctl_mon_addr[pll_idx]) & DDS_MASK; in _fhctl_mon_done()
172 pllidx2name(pll_idx), mon_dds, tar_dds); in _fhctl_mon_done()
191 static uint32_t _pll_get_postdiv_reg(uint32_t pll_idx) in _pll_get_postdiv_reg() argument
196 val = apupwr_readl(mixed_con1_addr[pll_idx]); in _pll_get_postdiv_reg()
219 static void _set_postdiv_reg(uint32_t pll_idx, uint32_t post_div) in _set_postdiv_reg() argument
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| H A D | apupwr_clkctl.c | 316 int32_t pll_idx; in apupwr_smc_bulk_pll() local
319 for (pll_idx = APUPLL; pll_idx < APUPLL_MAX; pll_idx++) { in apupwr_smc_bulk_pll()
320 ret = apu_pll_enable(pll_idx, enable, false); in apupwr_smc_bulk_pll()
326 for (pll_idx = APUPLL2; pll_idx >= APUPLL; pll_idx--) { in apupwr_smc_bulk_pll()
327 ret = apu_pll_enable(pll_idx, enable, false); in apupwr_smc_bulk_pll()
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| H A D | apupwr_clkctl.h | 20 int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en);
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| /rk3399_ARM-atf/plat/aspeed/ast2700/ |
| H A D | plat_bl31_setup.c | 140 static uint32_t plat_get_pll_rate(int pll_idx) in plat_get_pll_rate() argument
146 switch (pll_idx) { in plat_get_pll_rate()
157 ERROR("%s: invalid PSP clock source (%d)\n", __func__, pll_idx); in plat_get_pll_rate()
161 if (pll_idx == PLAT_CLK_HPLL && ((mmio_read_32(SCU_CPU_HW_STRAP1) & GENMASK(3, 2)) != 0U)) { in plat_get_pll_rate()
178 if (pll_idx == PLAT_CLK_MPLL) { in plat_get_pll_rate()
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/constraints/ |
| H A D | mt_spm_rc_api.c | 37 uint32_t pll_idx = cond_id - PLAT_SPM_COND_MAX; in spm_rc_condition_modifier() local
41 tlb->table_pll |= (cond << pll_idx); in spm_rc_condition_modifier()
43 tlb->table_pll &= ~(cond << pll_idx); in spm_rc_condition_modifier()
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| /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8188/ |
| H A D | apusys_power.c | 291 int pll_idx; in apu_pll_init() local
297 for (pll_idx = 0; pll_idx < PLL_NUM; pll_idx++) { in apu_pll_init()
298 mmio_setbits_32(APU_PLL_BASE + pll_hfctl_cfg[pll_idx], (FHCTL0_EN | SFSTR0_EN)); in apu_pll_init()
302 get_pll_pcw(pll_freq_out[pll_idx], &posdiv_val, &pcw_val); in apu_pll_init()
304 mmio_clrsetbits_32(APU_PLL_BASE + pll_con1[pll_idx], in apu_pll_init()
307 mmio_write_32(APU_PLL_BASE + pll_fhctl_dds[pll_idx], in apu_pll_init()
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/constraints/ |
| H A D | mt_spm_rc_api.c | 41 unsigned int pll_idx = cond_id - PLAT_SPM_COND_MAX; in spm_rc_condition_modifier() local
45 SPM_RC_BITS_SET(tlb->table_pll, (cond << pll_idx)); in spm_rc_condition_modifier()
47 SPM_RC_BITS_CLR(tlb->table_pll, (cond << pll_idx)); in spm_rc_condition_modifier()
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| /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/ |
| H A D | apusys_power.c | 163 int pll_idx, are_idx; in apu_pll_init() local
173 for (pll_idx = 0 ; pll_idx < ARRAY_SIZE(pll_base_arr) ; pll_idx++) { in apu_pll_init()
174 base_reg = APUSYS_PLL + pll_base_arr[pll_idx]; in apu_pll_init()
185 get_pll_pcw(pll_freq_out[pll_idx], &posdiv_val, &pcw_val); in apu_pll_init()
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| /rk3399_ARM-atf/drivers/st/clk/ |
| H A D | clk-stm32mp2.c | 1729 static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx) in clk_stm32_pll_get_pdata() argument
1734 return &pdata->pll[pll_idx]; in clk_stm32_pll_get_pdata()
1737 static int _clk_stm32_pll1_init(struct stm32_clk_priv *priv, int pll_idx, in _clk_stm32_pll1_init() argument
1740 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx); in _clk_stm32_pll1_init()
1790 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx, in _clk_stm32_pll_init() argument
1793 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx); in _clk_stm32_pll_init()
1829 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx) in clk_stm32_pll_init() argument
1831 struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx); in clk_stm32_pll_init()
1834 if (pll_idx == _PLL1) { in clk_stm32_pll_init()
1835 return _clk_stm32_pll1_init(priv, pll_idx, pll_conf); in clk_stm32_pll_init()
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| H A D | clk-stm32mp13.c | 1294 static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx) in clk_stm32_pll_get_pdata() argument
1299 return &pdata->pll[pll_idx]; in clk_stm32_pll_get_pdata()
1508 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx, in _clk_stm32_pll_init() argument
1511 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_idx); in _clk_stm32_pll_init()
1522 if ((pll_idx == _PLL4) && pll4_bootrom) { in _clk_stm32_pll_init()
1548 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx) in clk_stm32_pll_init() argument
1550 struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx); in clk_stm32_pll_init()
1553 return _clk_stm32_pll_init(priv, pll_idx, pll_conf); in clk_stm32_pll_init()
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| H A D | stm32mp1_clk.c | 2166 static int stm32mp1_pll_configure_src(struct stm32_clk_priv *priv, int pll_idx) in stm32mp1_pll_configure_src() argument
2169 struct stm32_pll_dt_cfg *pll_conf = &pdata->pll[pll_idx]; in stm32mp1_pll_configure_src()
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