127 static const char *pllidx2name(int32_t pll_idx)  in pllidx2name()  argument
137 	if (pll_idx >= APUPLL_MAX) {  in pllidx2name()
138 		pll_idx = APUPLL_MAX;  in pllidx2name()
141 	return names[pll_idx];  in pllidx2name()
157 static int32_t _fhctl_mon_done(uint32_t pll_idx, unsigned long tar_dds)  in _fhctl_mon_done()  argument
165 		mon_dds = apupwr_readl(fhctl_mon_addr[pll_idx]) & DDS_MASK;  in _fhctl_mon_done()
172 				  pllidx2name(pll_idx), mon_dds, tar_dds);  in _fhctl_mon_done()
191 static uint32_t _pll_get_postdiv_reg(uint32_t pll_idx)  in _pll_get_postdiv_reg()  argument
196 	val = apupwr_readl(mixed_con1_addr[pll_idx]);  in _pll_get_postdiv_reg()
219 static void _set_postdiv_reg(uint32_t pll_idx, uint32_t post_div)  in _set_postdiv_reg()  argument
221 	apupwr_clrbits(POSDIV_MASK << POSDIV_SHIFT, mixed_con1_addr[pll_idx]);  in _set_postdiv_reg()
223 			mixed_con1_addr[pll_idx]);  in _set_postdiv_reg()
275 static void _pll_en(uint32_t pll_idx, bool on)  in _pll_en()  argument
278 		apupwr_setbits(RG_PLL_EN, mixed_con0_addr[pll_idx]);  in _pll_en()
280 		apupwr_clrbits(RG_PLL_EN, mixed_con0_addr[pll_idx]);  in _pll_en()
293 static void _pll_pwr(uint32_t pll_idx, bool on)  in _pll_pwr()  argument
296 		apupwr_setbits(DA_PLL_SDM_PWR_ON, mixed_con3_addr[pll_idx]);  in _pll_pwr()
298 		apupwr_clrbits(DA_PLL_SDM_PWR_ON, mixed_con3_addr[pll_idx]);  in _pll_pwr()
312 static void _pll_iso(uint32_t pll_idx, bool enable)  in _pll_iso()  argument
315 		apupwr_setbits(DA_PLL_SDM_ISO_EN, mixed_con3_addr[pll_idx]);  in _pll_iso()
317 		apupwr_clrbits(DA_PLL_SDM_ISO_EN, mixed_con3_addr[pll_idx]);  in _pll_iso()
334 static int32_t _pll_switch(uint32_t pll_idx, bool on, bool fhctl_en)  in _pll_switch()  argument
338 	if (pll_idx >= APUPLL_MAX) {  in _pll_switch()
339 		ERROR("%s wrong pll_idx: %d\n", __func__, pll_idx);  in _pll_switch()
345 		_pll_pwr(pll_idx, true);  in _pll_switch()
347 		_pll_iso(pll_idx, false);  in _pll_switch()
349 		_pll_en(pll_idx, true);  in _pll_switch()
352 		_pll_en(pll_idx, false);  in _pll_switch()
353 		_pll_iso(pll_idx, true);  in _pll_switch()
354 		_pll_pwr(pll_idx, false);  in _pll_switch()
379 int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en)  in apu_pll_enable()  argument
383 	if (pll_idx >= APUPLL_MAX) {  in apu_pll_enable()
384 		ERROR("%s wrong pll_idx: %d\n", __func__, pll_idx);  in apu_pll_enable()
390 		switch (pll_idx) {  in apu_pll_enable()
394 				_pll_switch(pll_idx, enable, fhctl_en);  in apu_pll_enable()
402 				_pll_switch(pll_idx, enable, fhctl_en);  in apu_pll_enable()
410 				_pll_switch(pll_idx, enable, fhctl_en);  in apu_pll_enable()
418 				_pll_switch(pll_idx, enable, fhctl_en);  in apu_pll_enable()
424 			ERROR("%s invalid pll_idx: %d\n", __func__, pll_idx);  in apu_pll_enable()
429 		switch (pll_idx) {  in apu_pll_enable()
436 				_pll_switch(pll_idx, enable, fhctl_en);  in apu_pll_enable()
446 				_pll_switch(pll_idx, enable, fhctl_en);  in apu_pll_enable()
456 				_pll_switch(pll_idx, enable, fhctl_en);  in apu_pll_enable()
466 				_pll_switch(pll_idx, enable, fhctl_en);  in apu_pll_enable()
471 			ERROR("%s invalid pll_idx: %d\n", __func__, pll_idx);  in apu_pll_enable()
511 	int32_t pll_idx, ret = 0;  in anpu_pll_set_rate()  local
513 	pll_idx = vd2pllidx(domain);  in anpu_pll_set_rate()
514 	if (pll_idx < 0) {  in anpu_pll_set_rate()
515 		ret = pll_idx;  in anpu_pll_set_rate()
522 	     __func__, pllidx2name(pll_idx), pd, dds, freq / 1000, mode);  in anpu_pll_set_rate()
538 		apupwr_writel(pd, mixed_con1_addr[pll_idx]);  in anpu_pll_set_rate()
543 		_pll_en(pll_idx, false);  in anpu_pll_set_rate()
544 		apupwr_writel(dds, fhctl_dds_addr[pll_idx]);  in anpu_pll_set_rate()
545 		_set_postdiv_reg(pll_idx, pd);  in anpu_pll_set_rate()
546 		apupwr_setbits(PLL_TGL_ORG, fhctl_dds_addr[pll_idx]);  in anpu_pll_set_rate()
549 		_pll_en(pll_idx, true);  in anpu_pll_set_rate()
553 		old_pd = _pll_get_postdiv_reg(pll_idx);  in anpu_pll_set_rate()
555 			_set_postdiv_reg(pll_idx, pd);  in anpu_pll_set_rate()
556 			apupwr_writel(dds, fhctl_dvfs_addr[pll_idx]);  in anpu_pll_set_rate()
558 			apupwr_writel(dds, fhctl_dvfs_addr[pll_idx]);  in anpu_pll_set_rate()
559 			_set_postdiv_reg(pll_idx, pd);  in anpu_pll_set_rate()
561 		ret = _fhctl_mon_done(pll_idx, dds);  in anpu_pll_set_rate()