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Searched refs:dram_info (Results 1 – 8 of 8) sorted by relevance

/rk3399_ARM-atf/plat/imx/imx8m/ddr/
H A Ddram.c19 struct dram_info dram_info; variable
110 if (dram_info.dram_type == DDRC_LPDDR4) { in get_mr_values()
121 uint32_t pstate_num = dram_info.num_fsp; in save_rank_setting()
128 dram_info.rank_setting[i][0] = mmio_read_32(DDRC_DRAMTMG2(0) + offset); in save_rank_setting()
129 if (dram_info.dram_type != DDRC_LPDDR4) { in save_rank_setting()
130 dram_info.rank_setting[i][1] = mmio_read_32(DDRC_DRAMTMG9(0) + offset); in save_rank_setting()
133 dram_info.rank_setting[i][2] = mmio_read_32(DDRC_RANKCTL(0) + offset); in save_rank_setting()
137 dram_info.rank_setting[0][2] = mmio_read_32(DDRC_RANKCTL(0)); in save_rank_setting()
224 dram_info.dram_type = ddrc_mstr & DDR_TYPE_MASK; in dram_info_init()
225 dram_info.num_rank = ((ddrc_mstr >> 24) & ACTIVE_RANK_MASK) == 0x3 ? in dram_info_init()
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H A Ddram_retention.c29 uint32_t pstate_num = dram_info.num_fsp; in rank_setting_update()
36 mmio_write_32(DDRC_DRAMTMG2(0) + offset, dram_info.rank_setting[i][0]); in rank_setting_update()
37 if (dram_info.dram_type != DDRC_LPDDR4) { in rank_setting_update()
38 mmio_write_32(DDRC_DRAMTMG9(0) + offset, dram_info.rank_setting[i][1]); in rank_setting_update()
43 dram_info.rank_setting[i][2]); in rank_setting_update()
47 mmio_write_32(DDRC_RANKCTL(0), dram_info.rank_setting[0][2]); in rank_setting_update()
69 if (dram_info.dram_type == DDRC_LPDDR4) { in dram_enter_retention()
151 dram_umctl2_init(dram_info.timing_info); in dram_exit_retention()
168 if (dram_info.dram_type == DDRC_LPDDR4) { in dram_exit_retention()
176 dram_phy_init(dram_info.timing_info); in dram_exit_retention()
H A Dddr4_dvfs.c77 void dram_cfg_all_mr(struct dram_info *info, uint32_t pstate) in dram_cfg_all_mr()
161 void ddr4_swffc(struct dram_info *info, unsigned int pstate) in ddr4_swffc()
H A Dlpddr4_dvfs.c31 void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, in lpddr4_swffc()
/rk3399_ARM-atf/plat/imx/imx8m/include/
H A Ddram.h57 struct dram_info { struct
71 extern struct dram_info dram_info; argument
90 void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, unsigned int fsp_index);
91 void ddr4_swffc(struct dram_info *dram_info, unsigned int pstate);
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Ddram_spec_timing.c120 return max(timing_config->dram_info[0].speed_rate, in get_max_speed_rate()
121 timing_config->dram_info[1].speed_rate); in get_max_speed_rate()
123 return timing_config->dram_info[0].speed_rate; in get_max_speed_rate()
133 for (cs = 0; cs < timing_config->dram_info[ch].cs_cnt; cs++) { in get_max_die_capability()
136 dram_info[ch].per_die_capability[cs]); in get_max_die_capability()
H A Ddram_spec_timing.h183 struct dram_info_t dram_info[2]; member
H A Ddfs.c187 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; in sdram_timing_cfg_init()
188 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; in sdram_timing_cfg_init()
190 ptiming_config->dram_info[i].per_die_capability[j] = in sdram_timing_cfg_init()