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Searched refs:clk_id (Results 1 – 18 of 18) sorted by relevance

/rk3399_ARM-atf/drivers/ti/ti_sci/
H A Dti_sci.h150 int ti_sci_clock_get(uint32_t dev_id, uint8_t clk_id,
153 int ti_sci_clock_idle(uint32_t dev_id, uint8_t clk_id);
154 int ti_sci_clock_put(uint32_t dev_id, uint8_t clk_id);
155 int ti_sci_clock_is_auto(uint32_t dev_id, uint8_t clk_id,
157 int ti_sci_clock_is_on(uint32_t dev_id, uint8_t clk_id,
159 int ti_sci_clock_is_off(uint32_t dev_id, uint8_t clk_id,
161 int ti_sci_clock_set_parent(uint32_t dev_id, uint8_t clk_id,
163 int ti_sci_clock_get_parent(uint32_t dev_id, uint8_t clk_id,
165 int ti_sci_clock_get_num_parents(uint32_t dev_id, uint8_t clk_id,
167 int ti_sci_clock_get_match_freq(uint32_t dev_id, uint8_t clk_id,
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H A Dti_sci.c691 int ti_sci_clock_set_state(uint32_t dev_id, uint8_t clk_id, in ti_sci_clock_set_state() argument
710 req.clk_id = clk_id; in ti_sci_clock_set_state()
734 int ti_sci_clock_get_state(uint32_t dev_id, uint8_t clk_id, in ti_sci_clock_get_state() argument
757 req.clk_id = clk_id; in ti_sci_clock_get_state()
786 int ti_sci_clock_get(uint32_t dev_id, uint8_t clk_id, in ti_sci_clock_get() argument
796 return ti_sci_clock_set_state(dev_id, clk_id, flags, in ti_sci_clock_get()
812 int ti_sci_clock_idle(uint32_t dev_id, uint8_t clk_id) in ti_sci_clock_idle() argument
814 return ti_sci_clock_set_state(dev_id, clk_id, 0, in ti_sci_clock_idle()
830 int ti_sci_clock_put(uint32_t dev_id, uint8_t clk_id) in ti_sci_clock_put() argument
832 return ti_sci_clock_set_state(dev_id, clk_id, 0, in ti_sci_clock_put()
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H A Dti_sci_protocol.h300 uint8_t clk_id; member
321 uint8_t clk_id; member
359 uint8_t clk_id; member
376 uint8_t clk_id; member
407 uint8_t clk_id; member
450 uint8_t clk_id; member
506 uint8_t clk_id; member
524 uint8_t clk_id; member
/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_clk_utils.c11 unsigned long clk_id) in s32cc_clk_get_from_array() argument
15 type = S32CC_CLK_TYPE(clk_id); in s32cc_clk_get_from_array()
21 id = S32CC_CLK_ID(clk_id); in s32cc_clk_get_from_array()
32 unsigned long clk_id) in s32cc_get_clk_from_table() argument
38 clk = s32cc_clk_get_from_array(clk_arr[i], clk_id); in s32cc_get_clk_from_table()
/rk3399_ARM-atf/plat/nvidia/tegra/drivers/bpmp_ipc/
H A Dintf.c301 int tegra_bpmp_ipc_enable_clock(uint32_t clk_id) in tegra_bpmp_ipc_enable_clock() argument
307 if (clk_id != TEGRA_CLK_SE) { in tegra_bpmp_ipc_enable_clock()
312 req.cmd_and_id = make_mrq_clk_cmd(CMD_CLK_ENABLE, clk_id); in tegra_bpmp_ipc_enable_clock()
318 clk_id, ret); in tegra_bpmp_ipc_enable_clock()
324 int tegra_bpmp_ipc_disable_clock(uint32_t clk_id) in tegra_bpmp_ipc_disable_clock() argument
330 if (clk_id != TEGRA_CLK_SE) { in tegra_bpmp_ipc_disable_clock()
335 req.cmd_and_id = make_mrq_clk_cmd(CMD_CLK_DISABLE, clk_id); in tegra_bpmp_ipc_disable_clock()
341 clk_id, ret); in tegra_bpmp_ipc_disable_clock()
/rk3399_ARM-atf/plat/nvidia/tegra/include/drivers/
H A Dbpmp_ipc.h35 int tegra_bpmp_ipc_enable_clock(uint32_t clk_id);
41 int tegra_bpmp_ipc_disable_clock(uint32_t clk_id);
/rk3399_ARM-atf/drivers/st/clk/
H A Dstm32mp_clkfunc.c304 int clk_id; in fdt_get_uart_clock_freq() local
316 clk_id = fdt_get_clock_id(node); in fdt_get_uart_clock_freq()
317 if (clk_id < 0) { in fdt_get_uart_clock_freq()
321 return clk_get_rate((unsigned long)clk_id); in fdt_get_uart_clock_freq()
H A Dclk-stm32-core.c387 int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int clk_id) in _clk_stm32_get_parent() argument
389 const struct stm32_clk_ops *ops = _clk_get_ops(priv, clk_id); in _clk_stm32_get_parent()
394 mux_id = priv->clks[clk_id].parent; in _clk_stm32_get_parent()
407 sel = ops->get_parent(priv, clk_id); in _clk_stm32_get_parent()
419 int _clk_stm32_get_parent_index(struct stm32_clk_priv *priv, int clk_id) in _clk_stm32_get_parent_index() argument
423 mux_id = priv->clks[clk_id].parent; in _clk_stm32_get_parent_index()
437 int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx) in _clk_stm32_get_parent_by_index() argument
442 mux_id = priv->clks[clk_id].parent; in _clk_stm32_get_parent_by_index()
H A Dclk-stm32mp13.c862 uint16_t clk_id; member
1056 int clk_id; in stm32_clk_configure_clk() local
1059 clk_id = stm32_clk_configure_clk_get_binding_id(priv, data); in stm32_clk_configure_clk()
1060 if (clk_id < 0) { in stm32_clk_configure_clk()
1061 return clk_id; in stm32_clk_configure_clk()
1064 ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel); in stm32_clk_configure_clk()
1070 clk_stm32_enable_call_ops(priv, clk_id); in stm32_clk_configure_clk()
1072 clk_stm32_disable_call_ops(priv, clk_id); in stm32_clk_configure_clk()
1113 int clk_id; in stm32_clk_source_configure() local
1139 clk_id = stm32_clk_configure_clk_get_binding_id(priv, cmd_data); in stm32_clk_source_configure()
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H A Dclk-stm32mp2.c707 uint16_t clk_id; member
713 .clk_id = (_clk_id),\
802 pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcfgr1, in _clk_stm32_pll_wait_ready_on()
821 pll->clk_id - _CK_PLL1 + 1, pllxcfgr1, mmio_read_32(pllxcfgr1)); in _clk_stm32_pll_wait_ready_off()
1637 refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id); in clk_stm32_pll_config_output()
1751 refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id); in _clk_stm32_pll1_init()
1782 EARLY_ERROR("PLL%d ref clock not started\n", pll->clk_id - _CK_PLL1 + 1); in clk_stm32_pll_wait_mux_ready()
2136 int clk_id = 0; in stm32_clk_configure_clk() local
2139 clk_id = stm32_clk_configure_clk_get_binding_id(priv, data); in stm32_clk_configure_clk()
2140 if (clk_id < 0) { in stm32_clk_configure_clk()
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H A Dclk-stm32-core.h174 int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx);
175 int _clk_stm32_get_parent_index(struct stm32_clk_priv *priv, int clk_id);
/rk3399_ARM-atf/include/drivers/nxp/clk/s32cc/
H A Ds32cc-clk-utils.h13 unsigned long clk_id);
/rk3399_ARM-atf/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h47 #define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\ argument
49 ((clk_id) << CLK_ID_SHIFT) |\
H A Dstm32mp25-clksrc.h47 #define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\ argument
49 ((clk_id) << CLK_ID_SHIFT) |\
H A Dstm32mp13-clksrc.h85 #define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\ argument
86 (((clk_id) << CLK_ID_SHIFT) |\
89 #define CLK_DISABLED(clk_id) ((CMD_CLK << CMD_SHIFT) |\ argument
90 ((clk_id) << CLK_ID_SHIFT))
H A Dstm32mp15-clksrc.h51 #define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\ argument
52 ((clk_id) << CLK_ID_SHIFT) |\
55 #define CLK_DISABLED(clk_id) ((CMD_CLK << CMD_SHIFT) |\ argument
56 ((clk_id) << CLK_ID_SHIFT))
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_clock_manager.h305 uint32_t clkmgr_get_rate(uint32_t clk_id);
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_clock_manager.c606 uint32_t clkmgr_get_rate(uint32_t clk_id) in clkmgr_get_rate() argument
610 switch (clk_id) { in clkmgr_get_rate()