Lines Matching refs:clk_id
862 uint16_t clk_id; member
1056 int clk_id; in stm32_clk_configure_clk() local
1059 clk_id = stm32_clk_configure_clk_get_binding_id(priv, data); in stm32_clk_configure_clk()
1060 if (clk_id < 0) { in stm32_clk_configure_clk()
1061 return clk_id; in stm32_clk_configure_clk()
1064 ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel); in stm32_clk_configure_clk()
1070 clk_stm32_enable_call_ops(priv, clk_id); in stm32_clk_configure_clk()
1072 clk_stm32_disable_call_ops(priv, clk_id); in stm32_clk_configure_clk()
1113 int clk_id; in stm32_clk_source_configure() local
1139 clk_id = stm32_clk_configure_clk_get_binding_id(priv, cmd_data); in stm32_clk_source_configure()
1141 if (clk_id == _RTCCK) { in stm32_clk_source_configure()
1188 .clk_id = (_clk_id),\
1203 prate = _clk_stm32_get_parent_rate(priv, pll->clk_id); in clk_stm32_pll_compute_cfgr1()
1456 pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base)); in _clk_stm32_pll_wait_ready_on()
1474 pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base)); in _clk_stm32_pll_wait_ready_off()
1678 .clk_id = (_clk_id),\