126e2b93aSVarun Wadekar /* 2ff605ba2Ssteven kao * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*67db3231SVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 426e2b93aSVarun Wadekar * 526e2b93aSVarun Wadekar * SPDX-License-Identifier: BSD-3-Clause 626e2b93aSVarun Wadekar */ 726e2b93aSVarun Wadekar 8*67db3231SVarun Wadekar #ifndef BPMP_IPC_H 9*67db3231SVarun Wadekar #define BPMP_IPC_H 1026e2b93aSVarun Wadekar 116e756f6dSAmbroise Vincent #include <lib/utils_def.h> 1226e2b93aSVarun Wadekar #include <stdbool.h> 1326e2b93aSVarun Wadekar #include <stdint.h> 1426e2b93aSVarun Wadekar 1526e2b93aSVarun Wadekar /** 1626e2b93aSVarun Wadekar * Currently supported reset identifiers 1726e2b93aSVarun Wadekar */ 1826e2b93aSVarun Wadekar #define TEGRA_RESET_ID_XUSB_PADCTL U(114) 1926e2b93aSVarun Wadekar #define TEGRA_RESET_ID_GPCDMA U(70) 2026e2b93aSVarun Wadekar 2126e2b93aSVarun Wadekar /** 2226e2b93aSVarun Wadekar * Function to initialise the IPC with the bpmp 2326e2b93aSVarun Wadekar */ 2426e2b93aSVarun Wadekar int32_t tegra_bpmp_ipc_init(void); 2526e2b93aSVarun Wadekar 2626e2b93aSVarun Wadekar /** 2726e2b93aSVarun Wadekar * Handler to reset a module 2826e2b93aSVarun Wadekar */ 2926e2b93aSVarun Wadekar int32_t tegra_bpmp_ipc_reset_module(uint32_t rst_id); 3026e2b93aSVarun Wadekar 31ff605ba2Ssteven kao /** 32ff605ba2Ssteven kao * Handler to enable clock to a module. Only SE device is 33ff605ba2Ssteven kao * supported for now. 34ff605ba2Ssteven kao */ 35ff605ba2Ssteven kao int tegra_bpmp_ipc_enable_clock(uint32_t clk_id); 36ff605ba2Ssteven kao 37ff605ba2Ssteven kao /** 38ff605ba2Ssteven kao * Handler to disable clock to a module. Only SE device is 39ff605ba2Ssteven kao * supported for now. 40ff605ba2Ssteven kao */ 41ff605ba2Ssteven kao int tegra_bpmp_ipc_disable_clock(uint32_t clk_id); 42ff605ba2Ssteven kao 43*67db3231SVarun Wadekar #endif /* BPMP_IPC_H */ 44