| /rk3399_ARM-atf/plat/st/stm32mp2/ |
| H A D | bl2_plat_setup.c | 138 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) { in reset_backup_domain()
139 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in reset_backup_domain()
141 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) { in reset_backup_domain()
145 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in reset_backup_domain()
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| /rk3399_ARM-atf/plat/st/stm32mp1/ |
| H A D | bl2_plat_setup.c | 248 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { in bl2_el3_plat_arch_setup()
249 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in bl2_el3_plat_arch_setup()
251 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == in bl2_el3_plat_arch_setup()
256 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in bl2_el3_plat_arch_setup()
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| /rk3399_ARM-atf/drivers/st/clk/ |
| H A D | stm32mp1_clk.c | 172 MUX_CFG(MUX_RTC, RCC_BDCR, 16, 2),
671 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL),
765 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents),
1583 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { in stm32mp1_lse_enable()
1588 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); in stm32mp1_lse_enable()
1592 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); in stm32mp1_lse_enable()
1599 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> in stm32mp1_lse_enable()
1609 mmio_clrsetbits_32(rcc_base + RCC_BDCR, in stm32mp1_lse_enable()
1614 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); in stm32mp1_lse_enable()
1619 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { in stm32mp1_lse_wait()
[all …]
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| H A D | clk-stm32mp2.c | 344 MUX_CONF(MUX_RTC, rtc_src, RCC_BDCR, 16, 2),
482 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0),
486 GATE_CFG(GATE_LSI, RCC_BDCR, 9, 0),
488 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0),
500 GATE_CFG(GATE_LSI_RDY, RCC_BDCR, 10, 0),
502 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0),
663 BYPASS(RCC_BDCR, 1, 3),
664 CSS(RCC_BDCR, 8),
665 DRIVE(RCC_BDCR, 4, 2, 2)),
1091 uintptr_t address = priv->base + RCC_BDCR; in clk_stm32_osc_msi_set_rate()
[all …]
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| H A D | clk-stm32mp13.c | 428 MUX_CFG(MUX_RTC, RTC_src, RCC_BDCR, 16, 2),
608 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0),
609 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0),
616 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0),
1654 BYPASS(RCC_BDCR, 1, 3),
1655 CSS(RCC_BDCR, 8),
1656 DRIVE(RCC_BDCR, 4, 2, 2)),
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| /rk3399_ARM-atf/include/drivers/st/ |
| H A D | stm32mp13_rcc.h | 26 #define RCC_BDCR U(0X400) macro
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| H A D | stm32mp15_rcc.h | 49 #define RCC_BDCR U(0x140) macro
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| H A D | stm32mp21_rcc.h | 267 #define RCC_BDCR U(0x440) macro
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| H A D | stm32mp25_rcc.h | 268 #define RCC_BDCR U(0x440) macro
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