Lines Matching refs:RCC_BDCR
172 MUX_CFG(MUX_RTC, RCC_BDCR, 16, 2),
671 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL),
765 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents),
1583 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { in stm32mp1_lse_enable()
1588 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); in stm32mp1_lse_enable()
1592 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); in stm32mp1_lse_enable()
1599 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> in stm32mp1_lse_enable()
1609 mmio_clrsetbits_32(rcc_base + RCC_BDCR, in stm32mp1_lse_enable()
1614 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); in stm32mp1_lse_enable()
1619 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { in stm32mp1_lse_wait()
2079 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; in stm32_clk_configure_clk()
2088 mmio_setbits_32(priv->base + RCC_BDCR, RCC_BDCR_LSECSSON); in stm32_clk_configure_clk()