Searched refs:PSCI_CPU_PWR_LVL (Results 1 – 18 of 18) sorted by relevance
86 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_stats_update_pwr_down()120 local_state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; in psci_stats_update_pwr_up()121 stat_idx = get_stat_idx(local_state, PSCI_CPU_PWR_LVL); in psci_stats_update_pwr_up()124 residency = plat_psci_stat_get_residency(PSCI_CPU_PWR_LVL, in psci_stats_update_pwr_up()140 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_stats_update_pwr_up()205 if (pwrlvl > PSCI_CPU_PWR_LVL) { in psci_get_stat()209 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl < pwrlvl; lvl++) in psci_get_stat()
82 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL),184 if (end_pwrlvl == PSCI_CPU_PWR_LVL) { in psci_is_last_cpu_to_idle_at_pwrlvl()189 for (lvl = PSCI_CPU_PWR_LVL + U(1); lvl < end_pwrlvl; lvl++) { in psci_is_last_cpu_to_idle_at_pwrlvl()307 assert(pwrlvl > PSCI_CPU_PWR_LVL); in psci_set_req_local_pwr_state()308 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && in psci_set_req_local_pwr_state()342 assert(pwrlvl > PSCI_CPU_PWR_LVL); in psci_get_req_local_pwr_states()344 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && in psci_get_req_local_pwr_states()371 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= max_pwrlvl; lvl++) { in psci_update_req_local_pwr_states()399 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= max_pwrlvl; lvl++) { in psci_restore_req_local_pwr_states()462 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state(); in psci_get_target_local_pwr_states()[all …]
49 if (level > PSCI_CPU_PWR_LVL) { in psci_init_pwr_domain_node()149 while (level >= (int) PSCI_CPU_PWR_LVL) { in populate_power_domain_tree()179 if (level == (int) PSCI_CPU_PWR_LVL) { in populate_power_domain_tree()
28 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in psci_set_power_off_state()
113 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; in psci_cpu_suspend()141 psci_stats_update_pwr_up(cpu_idx, PSCI_CPU_PWR_LVL, &state_info); in psci_cpu_suspend()254 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) { in psci_affinity_info()
304 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]) != 0)); in psci_cpu_suspend_to_powerdown_finish()
106 assert((lvl >= PSCI_CPU_PWR_LVL) && (lvl <= PLAT_MAX_PWR_LVL)); in plat_psci_stat_get_residency()109 if (lvl == PSCI_CPU_PWR_LVL) in plat_psci_stat_get_residency()124 state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; in plat_psci_stat_get_residency()
94 for (i = (int)PLAT_MAX_PWR_LVL; i >= (int)PSCI_CPU_PWR_LVL; i--) { in armv8_2_get_pwr_afflv()375 for (i = PSCI_CPU_PWR_LVL; i <= aff_lvl; i++) { in armv8_2_validate_power_state()398 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = in armv8_2_get_sys_suspend_power_state()400 for (i = PSCI_CPU_PWR_LVL + 1; i <= PLAT_MAX_PWR_LVL; i++) { in armv8_2_get_sys_suspend_power_state()404 power_state = psci_make_powerstate(0, PSTATE_TYPE_STANDBY, PSCI_CPU_PWR_LVL); in armv8_2_get_sys_suspend_power_state()406 for (i = PSCI_CPU_PWR_LVL; i <= PLAT_MAX_PWR_LVL; i++) { in armv8_2_get_sys_suspend_power_state()
19 #define PLAT_CORE_LVL PSCI_CPU_PWR_LVL
102 for (int i = PLAT_MAX_PWR_LVL; i >= PSCI_CPU_PWR_LVL; i--) { in get_pwr_afflv()355 for (i = PSCI_CPU_PWR_LVL; i <= aff_lvl; i++) in validate_power_state()369 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) in get_sys_suspend_power_state()
239 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
128 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
291 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
307 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
31 #define PSCI_CPU_PWR_LVL U(0) macro
330 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { in plat_get_sys_suspend_power_state()
328 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { in plat_get_sys_suspend_power_state()
327 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { in plat_get_sys_suspend_power_state()