| #
ab5964aa |
| 26-Sep-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration
* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls102
Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration
* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls1028ardb board support
feat(plat/nxp/ls1028a): add ls1028a soc support
feat(plat/nxp/common): define default SD buffer
feat(driver/nxp/xspi): add MT35XU02G flash info
feat(plat/nxp/common): add SecMon register definition for ch_3_2
feat(driver/nxp/dcfg): define RSTCR_RESET_REQ
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
feat(plat/nxp/common): define default PSCI features if not defined
feat(plat/nxp/common): define common macro for ARM registers
feat(plat/nxp/common): add CCI and EPU address definition
show more ...
|
| #
3a2cc2e2 |
| 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
Define CPUECTLR_TIMER_2TICKS.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iecb5ed
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
Define CPUECTLR_TIMER_2TICKS.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iecb5ede82939e8502d2f1bc74ec3bfe2a00be65c
show more ...
|
| #
a2047853 |
| 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common): define default PSCI features if not defined
SoC code can define supported features, otherwise use default setting.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: J
feat(plat/nxp/common): define default PSCI features if not defined
SoC code can define supported features, otherwise use default setting.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I0f11498c1f7558ff0ec2d9b344f3f7a4f5489ced
show more ...
|
| #
35efe7a4 |
| 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common): define common macro for ARM registers
Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.
Signed-off-by: Bi
feat(plat/nxp/common): define common macro for ARM registers
Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I485661bfe3ed4f214c403ff6af53dc6af1ddf089
show more ...
|
| #
9719e19a |
| 24-Mar-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes I500ddbe9,I9c10dac9,I53bfff85,I06f7594d,I24bff8d4, ... into integration
* changes:
nxp lx2160a-aqds: new plat based on soc lx2160a
NXP lx2160a-rdb: new plat based on SoC lx2160a
Merge changes I500ddbe9,I9c10dac9,I53bfff85,I06f7594d,I24bff8d4, ... into integration
* changes:
nxp lx2160a-aqds: new plat based on soc lx2160a
NXP lx2160a-rdb: new plat based on SoC lx2160a
nxp lx2162aqds: new plat based on soc lx2160a
nxp: errata handling at soc level for lx2160a
nxp: make file for loading additional ddr image
nxp: adding support of soc lx2160a
nxp: deflt hdr files for soc & their platforms
nxp: platform files for bl2 and bl31 setup
nxp: warm reset support to retain ddr content
nxp: nv storage api on platforms
nxp: supports two mode of trusted board boot
nxp: fip-handler for additional fip_fuse.bin
nxp: fip-handler for additional ddr-fip.bin
nxp: image loader for loading fip image
nxp: svp & sip smc handling
nxp: psci platform functions used by lib/psci
nxp: helper function used by plat & common code
nxp: add data handler used by bl31
nxp: adding the driver.mk file
nxp-tool: for creating pbl file from bl2
nxp: adding the smmu driver
nxp: cot using nxp internal and mbedtls
nxp:driver for crypto h/w accelerator caam
nxp:add driver support for sd and emmc
nxp:add qspi driver
nxp: add flexspi driver support
nxp: adding gic apis for nxp soc
nxp: gpio driver support
nxp: added csu driver
nxp: driver pmu for nxp soc
nxp: ddr driver enablement for nxp layerscape soc
nxp: i2c driver support.
NXP: Driver for NXP Security Monitor
NXP: SFP driver support for NXP SoC
NXP: Interconnect API based on ARM CCN-CCI driver
NXP: TZC API to configure ddr region
NXP: Timer API added to enable ARM generic timer
nxp: add dcfg driver
nxp:add console driver for nxp platform
tools: add mechanism to allow platform specific image UUID
tbbr-cot: conditional definition for the macro
tbbr-cot: fix the issue of compiling time define
cert_create: updated tool for platform defined certs, keys & extensions
tbbr-tools: enable override TRUSTED_KEY_CERT
show more ...
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| #
dd4268a2 |
| 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: psci platform functions used by lib/psci
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9853263ed38fb2a9f04b9dc7d768942e32074719
|