| #
baf2e39f |
| 08-Aug-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration
* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
ref
Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration
* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
refactor(versal-net): use the generic GIC driver
show more ...
|
| #
8a4a551c |
| 30-Jun-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor(versal-net): use the generic GIC driver
With the introduction of USE_GIC_DRIVER, platforms no longer have to do
their own GIC management for basic PSCI-related operations. Previously a
half
refactor(versal-net): use the generic GIC driver
With the introduction of USE_GIC_DRIVER, platforms no longer have to do
their own GIC management for basic PSCI-related operations. Previously a
half-measure was possible by using plat_gicv3_base.c to get semi-generic
helpers which versal_net uses.
Since USE_GIC_DRIVER is based on plat_gicv3_base.c, convert the platform
to use that so its code is more generic. Expected benefits are slightly
better performance around calling the gic hooks on cpu suspend and less
platform code.
Change-Id: I8e8a92fd4111e4a83c7a34bc5255d924bc54e769
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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|
| #
bc11248a |
| 26-May-2025 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_versal_misra_fixes_series_3" into integration
* changes:
fix(xilinx): resolve misra rule 16.3 violations
fix(xilinx): resolve misra rule 2.5 violations
fix(xilin
Merge changes from topic "xlnx_versal_misra_fixes_series_3" into integration
* changes:
fix(xilinx): resolve misra rule 16.3 violations
fix(xilinx): resolve misra rule 2.5 violations
fix(xilinx): resolve misra rule 4.6 violations
fix(xilinx): resolve misra rule 12.2 violations
fix(xilinx): resolve misra rule 10.1 violations
fix(xilinx): resolve misra rule 8.13 violations
fix(xilinx): resolve misra rule 4.5 violations
fix(xilinx): resolve misra rule 16.4 violations
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|
| #
2993166d |
| 09-Apr-2025 |
Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com> |
fix(xilinx): resolve misra rule 4.5 violations
Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.4.5:
- Identifiers in the same name space with overlapping visibility should
be ty
fix(xilinx): resolve misra rule 4.5 violations
Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.4.5:
- Identifiers in the same name space with overlapping visibility should
be typographically unambiguous.
- Fix:
- Renamed PM_RET_ERROR_NOFEATURE to PM_RET_ERROR_IOCTL_NOT_SUPPORTED
and removed unnecessary macro definitions.
Change-Id: I6f03e619979685df7418fbccad7b0934d136776e
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>
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|
| #
1064bc6c |
| 22-Jan-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "idling-during-subsystem-restart" into integration
* changes:
fix(xilinx): add console_flush() before shutdown
fix(xilinx): fix sending sgi to linux
feat(xilinx): add
Merge changes from topic "idling-during-subsystem-restart" into integration
* changes:
fix(xilinx): add console_flush() before shutdown
fix(xilinx): fix sending sgi to linux
feat(xilinx): add new state to identify cpu power down
feat(xilinx): request cpu power down from reset
feat(xilinx): power down all cores on receiving cpu pwrdwn req
feat(xilinx): add handler for power down req sgi irq
feat(xilinx): add wrapper to handle cpu power down req
fix(versal-net): use arm common GIC handlers
fix(xilinx): rename macros to align with ARM
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|
| #
b2259261 |
| 06-Oct-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(versal-net): use arm common GIC handlers
Currently SGI interrupts are not received in secondary cores because
of issue in GIC configuration. In current Versal NET specific GIC
functions, redist
fix(versal-net): use arm common GIC handlers
Currently SGI interrupts are not received in secondary cores because
of issue in GIC configuration. In current Versal NET specific GIC
functions, redistributor configuration is not happening properly.
Because of that SGI interrupt from one processor to another processor
is not transferring. So, use common GIC handlers which will iterate
over all GIC redistributor frames and discovers per cpu redistributor
frame. Also, it initializes corresponding interface in GICv3.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I1433260b8520d6a315fdf5df86bd0688f92d211a
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|
| #
d84171b4 |
| 20-Apr-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "style(xilinx): replace ARM by Arm in copyrights" into integration
|
| #
619bc13e |
| 14-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
style(xilinx): replace ARM by Arm in copyrights
The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure
style(xilinx): replace ARM by Arm in copyrights
The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.
Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>
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|
| #
41c549f1 |
| 28-Mar-2023 |
Mark Dykes <mark.dykes@arm.com> |
Merge "refactor(xilinx): move pm_defs.h to common place" into integration
|
| #
92f7de1e |
| 03-Feb-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
refactor(xilinx): move pm_defs.h to common place
Moved pm_defs.h file to common place so that it can be used for
Versal NET and ZynqMP. Also moved common code from zynqmp_pm_defs.h to
common place.
refactor(xilinx): move pm_defs.h to common place
Moved pm_defs.h file to common place so that it can be used for
Versal NET and ZynqMP. Also moved common code from zynqmp_pm_defs.h to
common place.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I2ee1e72258c6052cdd6467cdbcf4009afb98da49
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|
| #
b97b2817 |
| 04-Oct-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(versal-net): use api_id directly without FUNCID_MASK" into integration
|
| #
b0eb6d12 |
| 03-Oct-2022 |
Michal Simek <michal.simek@amd.com> |
fix(versal-net): use api_id directly without FUNCID_MASK
The purpose of this code is to extract api_id from smc_fid but this masking
is done already in the code with using generic mask from smccc.h
fix(versal-net): use api_id directly without FUNCID_MASK
The purpose of this code is to extract api_id from smc_fid but this masking
is done already in the code with using generic mask from smccc.h
(FUNCID_NUM_MASK). That's why remove FUNCID_MASK is which not needed and
actually also equal to already used FUNCID_NUM_MASK.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I1113825baa5d9d58d9d7c5d9d5855fecf62e8d45
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|
| #
f47d38ba |
| 21-Sep-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xilinx-versal-net" into integration
* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP s
Merge changes from topic "xilinx-versal-net" into integration
* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP support for Versal NET
feat(versal-net): add support for Xilinx Versal NET platform
feat(versal-net): add documentation for Versal NET SoC
show more ...
|
| #
8529c769 |
| 19-Sep-2022 |
Michal Simek <michal.simek@amd.com> |
feat(versal-net): add SMP support for Versal NET
Add SMP support for Versal NET via register access.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare
feat(versal-net): add SMP support for Versal NET
Add SMP support for Versal NET via register access.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I46d73e2cd678ae720b5255722b6b0611c22659e8
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|
| #
1d333e69 |
| 31-Aug-2022 |
Michal Simek <michal.simek@amd.com> |
feat(versal-net): add support for Xilinx Versal NET platform
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx P
feat(versal-net): add support for Xilinx Versal NET platform
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410
show more ...
|